Search

In0.53Ga0.47As p + n diodes with different densities of extended defects have been analyzed by detailed structural and electrical characterization. The defects have been introduced during Metal-Organic Vapor Phase Epitaxy (MOVPE) growth by using a lattice-mismatched layer on a semi-insulating InP or GaAs substrate. The residual strain and indium content in the n-type In0.53Ga0.47As layer have been determined by high-resolution X-ray diffraction, showing nearly zero strain and a fixed indium ratio of 0.53. The deep levels in the layer have been characterized by Deep Level Transient Spectroscopy. The mean value of electron traps at 0.17 ± 0.03 eV below the conduction band minimum EC is assigned to the "localized" states of α 60° misfit dislocations; another broad electron trap with mean activation energies between EC− 0.17 ± 0.01 and 0.39 ± 0.04 eV, is identified as threading dislocation segments with "band-like" states. A high variation of the pre-exponential factor KT by 7 orders of magnitude is found for the latter when changing the filling pulse time, which can be explained by the coexistence of acceptor-like and donor-like states in the core of split dislocations in III-V materials. Furthermore, two hole traps at EV+ 0.42 ± 0.01 and EV+ 0.26 ± 0.13 eV are related to the double acceptor of the Ga(In) vacancy (VGa/In3-/2-) and 60° β misfit dislocations, respectively. Finally, the dislocation climbing mechanism and the evolution of the antisite defects AsGa/In are discussed for n-type In0.53Ga0.47As. [ABSTRACT FROM AUTHOR]

Herein, the carrier lifetime in ≈5 × 1016 cm−3 n‐doped InxGa1−xAs layers is studied by diode current–voltage analysis and by time‐resolved photoluminescence. Two sets of hetero‐epitaxial layers are grown on semi‐insulating InP or GaAs substrates. The first set corresponds with a constant In content p + n stack, while the second set has a fixed x = 0.53 for the n‐layer, while containing various extended defect densities by using a strain relaxed buffer with different x. This results in threading dislocation densities (TDDs) between ≈105 cm−2 and a few 109 cm−2. It is shown that the overall trend of the recombination lifetime versus TDD can be described by a first‐order model considering a finite recombination lifetime value inside a dislocation core of 1 nm. For the generation lifetime, a strong electric‐field enhancement factor is found. Also, the residual strain in the n‐layer has an impact. Overall, the safe limit for TDD depends on the type of application and on the operation conditions (reverse diode bias). [ABSTRACT FROM AUTHOR]

The impact of strain on negative bias temperature instability (NBTI) is assessed by studying devices with polycrystalline-Si/SiON as well as deposited metal gate/high-[kappa] and FUSI/high-[kappa] gate stacks. The studies have shown that there is no degradation of intrinsic NBTI behavior due to process-induced strain.

Influence of the gate module on the channel stress in [Si. Sub. 1-x] [Ge.sub.x] and [Si.sub.1-y] [C.sub.y] S/D MOS transistors are studied by simulation tests. Metal gates of 1nm thickness are found to influence stress generation and the removal and redeposition of polysilicon layer without changing the underlying metal gate increases the stress but not to the extent of complete gate removal.

The analysis of the junction leakage in heavily doped p+/n germanium junctions, targeted for short-channel transistor fabrication is described. The studies have shown that the area-junction static-power consumption for the best junctions has remained below the power-density specifications for high-performances applications.

The quality of ultrathin SiON dielectrics of n-type metal-oxide-semiconductor field-effect transistor (nMOSFET) grown on strained-Si layers with both thin and thick SiGe strain-relaxed buffers (SRBs) is examined. Results suggest that the gate leakage in the strained-Si samples was of a trap-assisted nature and temperature-dependent.

The fabrication of long-channel Ge transistors with a high-k dielectric and a hole mobility more than 2.5 times the Si/Si[O.sub.2] universal at vertical effective fields up to 1 MV/cm is reported.

A study on the effectiveness of strained contact-etches-stop-layer (CESL) technologies in aggressively scaled dense structures is presented. Results show that the two main channel stress components introduced by CESL, which are the vertical and parallel stresses, have a different sensitivity toward layout variations.

The performance and reliability between polysilicon gate/SiON oxide nano metal-oxide semiconductor field-effect transistors (nMOSFETs) is compared with and without SiN cap layer. The robustness against hot carrier stress, bias-temperature instability and time to breakdown are seen between strained and unstrained-silicon devices, thereby confirming the advantages of strain technology.

The layout dependence of the silicon-germanium source/drain {[Si.sub.1-x][Ge.sub.x] S/D} technology is studied for the 45-nm technology node and beyond. The nested transistor, where other gates surround a polygate and isolated transistors, where the active area is completely surrounded by isolation oxide are two technologically important configurations investigated.

The impact of different processing factors on the low-frequency (LF) noise of nMOSFETs fabricated in strained-silicon (SSi) substrates is analyzed. A better 1/f noise performance can be achieved using SSi substrates and some dedicated defect-assisted noise-generating mechanisms are identified, which are related to nonoptimized processing conditions.

The conduction and valence band offsets between a strained silicon-germanium layer and a silicongermanium substrate are reported for arbitrary substrate and channel crystal orientations. The offsets are calculated both for the case of biaxial stress, corresponding approximately to the stress state of a thin strained channel in a planar field-effect transistor (FET), and for uniaxial stress, which is the approximate stress state for strained channels in a FinFET configuration. Significant orientation dependence is found for the conduction band offset, overall leading to the strongest electron quantum confinement in biaxial-tensile stressed channels on {100}-oriented substrates, and uniaxialtensile stressed channels in the ⟨100⟩ and ⟨101⟩ directions. For biaxially stressed layers on {111} substrates, the conduction band offset is significantly smaller than for {100} or {110} directions. For the valence band offset, the dependence on crystal orientation is found to be small. [ABSTRACT FROM AUTHOR]