Search

Radiation hardening by design (RHBD) is traditionally performed using triple modular redundancy (TMR), a very effective technique that introduces high overheads in terms of resources and power. The reduced resolution redundancy (RRR) technique presented in this work is a new approximate error mitigation technique that uses redundant circuits with lower resolution to perform computations. In this work, we evaluate this technique under radiation using two different benchmarks implemented in field-programmable gate array (FPGA), namely, a fast Fourier transform (FFT) and an image processing algorithm for a near-infrared (NIR) detector. Experimental results from proton and neutron irradiation, and fault injection campaigns, show that the RRR hardening technique can effectively mitigate errors with reduced overheads.

This work presents the evaluation of a new dualcore lockstep hybrid approach aimed to improve the fault tolerance in microprocessors. Our approach takes advantage of modern multicore processor resources to combine a software-based lockstep with a custom hardware observer. The first is used to duplicate data and instruction flows; meanwhile, the second is in charge of the control-flow monitoring. The proposal has been implemented in a dualcore ARM microprocessor and validated with low energy proton irradiation and emulated fault injection campaigns. The results show an improvement of one order of magnitude in the cross-section of the benchmarks tested, even considering the worst-case scenario.

Reduced precision redundancy (RPR) is an alternative to triple modular redundancy (TMR) that reduces the area overhead at the expense of minor accuracy loss in case of error. In this work, we propose a Scaled RPR approach for multistage circuits and analyze the error mitigation tradeoffs. As a case study, several fast Fourier transform designs were tested with low-energy protons and fault injection. Experimental results show that the proposed approach achieves error mitigation with good accuracy, while significantly reducing the area overhead with respect to a full precision TMR approach.

Graphic processing units (GPUs) have become a basic accelerator both in high-performance nodes and low-power system-on-chip (SoC). They provide massive data parallelism and very high performance per watt. However, their reliability in harsh environments is an important issue to take into account, especially for safety-critical applications. In this article, we evaluate the influence of the parallelization strategy on the reliability of lower–upper (LU) decomposition on a GPU-accelerated SoC under proton irradiation. Specifically, we compare a memory bound and a compute bound implementation of the decomposition on a K20A GPU embedded on a Tegra K1 (TK1) SoC. We leverage the GPU and CPU clock frequencies both to highlight the radiation sensitivity of the GPU where we are running the benchmark and also to apply both algorithms to solve problems with the same size when exposed to the same radiation dose. Results show that more intensive use of the resources of the GPU increases the cross section. We also observed that most of the radiation-induced errors hang the operating system and even the rebooting process. Finally, we present a preliminary study of the error propagation of the LU decomposition algorithms.

This work presents the evaluation of a new dual-core lockstep hybrid approach aimed to improve the fault tolerance in microprocessors. Our approach takes advantage of modern multicore processor resources to combine software-based lockstep with a custom hardware observer. The first is used to duplicate data and instruction flows; meanwhile, the second is in charge of the control-flow monitoring. The proposal has been implemented in a dual-core ARM microprocessor and validated with low-energy proton irradiation and emulated fault injection campaigns. The results show an improvement of one order of magnitude in the cross section of the benchmarks tested, even considering the worst case scenario.

Nowadays, high-performance microprocessors are demanded in many fields, including those with high-reliability requirements. Commercial microprocessors present a good tradeoff between cost, size, and performance, albeit they must be adapted to satisfy the reliability requirements when they are used in harsh environments. This work presents a high-end multiprocessor hardened with macrosynchronized lockstep and additional protections. A commercial dual-core Advanced RISC Machine (ARM) cortex A9 has been used as a case study and a complete hardened system has been developed. Evaluation of the proposed hardened system has been accomplished with exhaustive fault injection campaigns and proton irradiation. The hardening approach has been accomplished for both baremetal applications and operating system (OS)-based. The hardened system has demonstrated high reliability in all performed experiments with error coverage up to 99.3% in the irradiation experiments. Experimental irradiation results demonstrate a cross-sectional reduction of two orders of magnitude.

This work analyzes the performance of the reduced precision redundancy (RPR) error mitigation technique using the fast Fourier transform (FFT) as a case study. To this purpose, several configurations of an FFT IP design were implemented in field-programmable gate array (FPGA) using reduced precision triple modular redundancy (RP-TMR) and tested under proton irradiation and fault injection. The cross section, the sensitivity to common-mode failures (CMFs), and the signal-to-noise ratio of these configurations were evaluated. The results of the radiation experiments and fault injection campaigns are in agreement and show that the RP-TMR technique may be used as an alternative to triple modular redundancy (TMR) if small errors can be tolerated, as it has a good performance in terms of error correction capabilities, area usage, and sensitivity to critical errors.

Studying the radiation effects on electronic devices is essential for avionics and space systems. The shrinking technology nodes and increasing density of devices enhance the sensitivity of electronic systems to ionizing radiation. Due to their crucial role, memories and processors are the highest contributors to soft errors in systems, making them the best candidates for studying these effects. This work introduces the radiation environment in space and atmosphere and the main effects that the different types of ionizing particles that are present in these environments may produce on electronic devices. Furthermore, mainly focusing on Single-Event Effects (SEEs), it presents approaches and tools for modeling SEEs and their impact on memories and microprocessors. Additionally, experimental results targeting a Commercial-Off-The-Shelf self-refresh Dynamic RAM are presented. These experiments are based on radiation test campaigns in particle accelerators with neutrons and protons. Finally, an overview of issues and mitigation techniques for microprocessors is exposed.