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A dynamic scaling (DS) method is proposed as a cost-effective means of eliminating overflow and limit cycle oscillations in fixed-point direct-form recursive filters. It is implemented by adding a DS unit to a fixed-point on-line module without modifying latter. On-line modules consume inputs and produce outputs digit serially, most significant digit first. The DS method introduces a shared exponent into the fixed-point computation at reasonable cost. Implementation in a 1.5 [Mu] gate array shows that the DS method is twice as cost effective as the previously known precision extension method. The need for scaling between filter sections is also eliminated. Index Terms - On-line arithmetic, oscillations, recursive digital filters.

The variable-precision classification (VPC) enhances the speed of vector quantization (VQ) by a serial-wise evaluation of the most significant bit. The average necessary precision is asymptotically independent of the operand precision when the operand precision increases. The codevector element's precision for the classification is less than four bits in VQ of real images. A comparison between VPC and conventional approaches for binary classification of circuiting reveals that VPC reduces computation complexity when the overall execution time is important.

This paper presents a new scheme for evaluating complex reciprocal and exponential functions in hardware. The proposed method utilizes a two-dimensional convolution algorithm to interpolate bivariate functions from tabulated function values in the complex domain. To reduce the memory requirements for lookup tables, the interpolation is decomposed into independent row and column computations, such that the same coefficient table can be shared. Three different interpolation kernels from degree-1 (linear) to degree-2 (quadratic Lagrange) and degree-3 (cubic Lagrange) are explored to find the optimal design parameters and the most acceptable trade-offs between performance and hardware resources. Moreover, a generic hardware architecture is designed to provide scalable implementation capabilities for computation precision and interpolation degree. To verify the proposed architecture, eight complex reciprocal and eight complex exponential design instances are implemented. The ASIC- and FPGA-based experimental results show that the proposed scheme can efficiently approximate the complex reciprocal and exponential functions with up to 16-bit precision, as well as achieve a considerable reduction of memory requirements compared with traditional bipartite and multipartite schemes. The proposed method is also applicable to other complex functions. [ABSTRACT FROM AUTHOR]