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Nowadays, artificial neural networks (ANNs) can outperform the human brain’s ability in specific tasks. However, ANNs cannot replicate the efficient and low-power learning, adaptation, and consolidation typical of biological organisms. Here, we present a hardware design based on arrays of SiOx resistive switching random-access memory (RRAM), which allows combining the accuracy of convolutional neural networks with the flexibility of bio-inspired neuronal plasticity. In order to enable the combination of the stable and the plastic attributes of the network, we exploit the spike-frequency adaptation of the neurons relying on the multilevel programming of the RRAM devices. This procedure enhances the efficiency and accuracy of the network for MNIST, noisy MNIST (N-MNIST), Fashion-MNIST, and CIFAR-10 datasets, with inference accuracies of about 99%–89%, respectively. We also demonstrate that the hardware is capable of asynchronous self-adaptation of its operative frequency according to the fire rate of the spiking neuron, thus optimizing the whole behavior of the network. We finally show that the system enables fast and accurate filter retraining to overcome catastrophic forgetting, showing high efficiency in terms of operations per second and robustness against device non-idealities. This work paves the way for the theoretical modeling and hardware realization of resilient autonomous systems in dynamic environments.

Volatile resistive switching random access memory (RRAM) devices are drawing attention in both storage and computing applications due to their high ON-/ OFF-ratio, fast switching speed, low leakage, and scalability. However, these devices are relatively new and the physical switching mechanisms are still under investigation. A thorough understanding and modeling of the physical dynamics underlying filament formation and self-dissolution are of utmost importance in view of future integration of volatile devices in neuromorphic systems and in memory arrays. To assess the physical mechanisms and develop appropriate models, though, the electrical properties of the device have to be characterized. In this article, we present an extensive study of Ag/SiO x -based volatile RRAM devices. Important parameters, such as switching time, switching voltage, and retention time are investigated as a function of the stimulation conditions. A physical explanation is provided and the applicability of the device in neuromorphic systems is discussed.

Understanding the switching mechanism of the volatile resistive switching random access memory (RRAM) device is important to harness its characteristics and further enhance its performance. Accurate modeling of its dynamic behavior is also of deep value for its applications both as selector and as short-term memory synapse for future neuromorphic applications operating in temporal domain. In this work, we investigate the switching and retention (relaxation) processes of the Ag-based metallic filamentary volatile resistive switching devices. We find that the switching process can be modeled by the ionic drift under electric field, while the retention process can be modeled by the ionic diffusion along the filament surface driven by the gradient of surface atomic concentration. Through further theoretical analysis, we also find that the ionic drift and ionic diffusion can be unified within the general Einstein relation. To confirm this relation, we collect ionic mobility and diffusivity data from the literature using the switching and retention model. Finally, we show that the read voltage dependent retention time can be explained by the competition between the ionic drift and diffusion flux.

A 'Women in Circuits and Systems' (WiCAS) event and a 'Young Professionals' (YP) event took place during the 27th Institute of Electrical and Electronics Engineers (IEEE) International conference on electronics circuits and systems (ICECS), the flagship conference for the Region 8 of the IEEE Circuits and Systems Society (CASS). The WiCAS events traditionally aim to inspire and motivate both students and young professionals in the domain of circuits and systems to have efficient roles in their professions, by meeting successful female engineers and professors, through interesting technical and professional talks in fields of interest of CASS. The YP events usually include start-ups presentation, poster and demo sessions, aiming to provide a thrilling environment for early career researchers to present their work. Joining this event, young professionals have the opportunity to learn about state of the art and most advanced activities in the area of circuits and systems, meet and interact with their peers, receive feedback from internationally well-known experts in the CASS domain from both academia and industry.

Wearable devices are a fast-growing technology with impact on personal healthcare for both society and economy. Due to the widespread of sensors in pervasive and distributed networks, power consumption, processing speed, and system adaptation are vital in future smart wearable devices. The visioning and forecasting of how to bring computation to the edge in smart sensors have already begun, with an aspiration to provide adaptive extreme edge computing. Here, we provide a holistic view of hardware and theoretical solutions toward smart wearable devices that can provide guidance to research in this pervasive computing era. We propose various solutions for biologically plausible models for continual learning in neuromorphic computing technologies for wearable sensors. To envision this concept, we provide a systematic outline in which prospective low power and low latency scenarios of wearable sensors in neuromorphic platforms are expected. We successively describe vital potential landscapes of neuromorphic processors exploiting complementary metal-oxide semiconductors (CMOS) and emerging memory technologies (e.g., memristive devices). Furthermore, we evaluate the requirements for edge computing within wearable devices in terms of footprint, power consumption, latency, and data size. We additionally investigate the challenges beyond neuromorphic computing hardware, algorithms and devices that could impede enhancement of adaptive edge computing in smart wearable devices., Frontiers in Neuroscience, 15, ISSN:1662-453X, ISSN:1662-4548

Motion detection is a primary visual function, crucial for the survival of animals in nature. Direction‐selective (DS) neurons can be found in multiple locations in the visual neural system, both in the retina and in the visual cortex. For instance, the DS ganglion cell in the retina provides a real‐time response to moving objects, which is much faster than the image recognition executed in the visual cortex. Such in‐retina biological signal processing capability is enabled by the spatiotemporal correlation within different receptive fields of the DS ganglion cells. Taking inspiration from the biological DS ganglion cells in the retina, the motion detection is demonstrated in an artificial neural network made of volatile resistive switching devices with short‐term memory effects. The motion detection arises from the spatiotemporal correlation between the adjacent excitatory and inhibitory receptive fields with short‐term memory synapses, closely resembling the physiological response of DS ganglion cells in the retina. The work supports real‐time neuromorphic processing of sensor data by exploiting the unique physics of innovative memory devices.

Ferroelectric tunneling junctions (FTJ) are considered to be the intrinsically most energy efficient memristors. In this work, specific electrical features of ferroelectric hafnium-zirconium oxide based FTJ devices are investigated. Moreover, the impact on the design of FTJ-based circuits for edge computing applications is discussed by means of two example circuits.

Biological systems autonomously evolve to maximize their efficiency in a continually changing world. On the other hand, artificial neural networks (ANNs) outperform the human ability of object recognition but cannot acquire new information without forgetting trained tasks. To introduce resilience in ANNs, we present a SiO x RRAM-based inference hardware capable of merging the efficiency of convolutional ANNs and the plasticity of spiking networks. We validate the accuracy of the system with MNIST (99.3%), noisyN-MNIST (96%), Fashion-MNIST (93%) and CIFAR-10 (91 %) datasets. We demonstrate that the circuit plastically adapts its operative frequency for power saving and enables continual learning of up to 50% non-trained classes. This optimizes the classification and enables the re-training of the filters, thus overcoming the catastrophic forgetting of standard ANN s.

The understanding of the dynamic mechanism of volatile resistive switching memory devices is of paramount importance to further increase the switching speed. It is also of great value for future neuromorphic applications which use such devices in temporal domain. In this work, we investigate the switching speed and retention time of metallic filamentary volatile resistive switching devices. We find that the switching speed can be quantitatively described by the ionic mobility, while the retention time can be quantitatively described by the surface ionic diffusion following the gradient descent of surface atomic concentration. Further analysis reveals that the ionic mobility and surface diffusivity can be connected with Einstein relation. Finally, evidences supporting this relation and experimental data showing the competition of the ionic drift and diffusion are collected and shown.

Neuromorphic computing has emerged as a promising approach for autonomous systems able to learn, adapt, and interact in real time with the environment. To build neuromorphic hardware, the recent development of novel material-based devices such as resistive switching memory (RRAM) has shown to be crucial since this class of devices offers the unique advantage to implement neuron and synaptic functions in silico by device physics, thus avoiding bulky circuits and very complex algorithms. In this work, we first explore volatile switching behaviour of RRAM devices, investigating their ability to capture short-term plasticity (STP) and short-term memory (STM) functionalities. Then, we characterise a volatile RRAM synapse, discussing its potential use in a spiking neural network for speech recognition applications.

Spiking neural networks (SNNs) employing memristive synapses are capable of life-long online learning. Because of their ability to process and classify large amounts of data in real-time using compact and low-power electronic systems, they promise a substantial technology breakthrough. However, the critical issue that memristor-based SNNs have to face is the fundamental limitation in their memory capacity due to finite resolution of the synaptic elements, which leads to the replacement of old memories with new ones and to a finite memory lifetime. In this study we demonstrate that the nonlinear conductance dynamics of memristive devices can be exploited to improve the memory lifetime of a network. The network is simulated on the basis of a spiking neuron model of mixed-signal digital-analogue sub-threshold neuromorphic CMOS circuits, and on memristive synapse models derived from the experimental nonlinear conductance dynamics of resistive memory devices when stimulated by trains of identical pulses. The network learning circuits implement a spike-based plasticity rule compatible with both spike-timing and rate-based learning rules. In order to get an insight on the memory lifetime of the network, we analyse the learning dynamics in the context of a classical benchmark of neural network learning, that is hand-written digit classification. In the proposed architecture, the memory lifetime and the performance of the network are improved for memristive synapses with nonlinear dynamics with respect to linear synapses with similar resolution. These results demonstrate the importance of following holistic approaches that combine the study of theoretical learning models with the development of neuromorphic CMOS SNNs with memristive devices used to implement life-long on-chip learning.

Volatile resistive switching memory (RRAM) is raising strong interest as potential selector device in crosspoint memory and short-term synapse in neuromorphic computing. To enable the design and simulation of memory and computing circuits with volatile RRAM, compact models are essential. To fill this gap, we present here a novel physics-based analytical model for volatile RRAM based on a detailed study of the switching process by molecular dynamics (MD) and finite-difference method (FDM). The analytical model captures all essential phenomena of volatile RRAM, e.g., threshold/holding voltages, on-off ratio, and size-dependent retention. The model is validated by extensive comparison with data from Ag/SiO x ), RRAM. To support the circuit-level capability of the model, we show simulations of crosspoint arrays and neuromorphic time-correlated learning.

Biologically plausible neuromorphic computing systems are attracting considerable attention due to their low latency, massively parallel information processing abilities, and their high energy efficiency. To achieve these features neuromorphic silicon neuron circuits need to be integrated with plastic synapse circuits capable of on-line learning and storage of synaptic weights. Within this context, memristive devices play a key role thanks to their nonvolatility, scalability, and compatibility with the complementary metal–oxide–semiconductor fabrication process. However, neuro-memristive systems are still facing difficult challenges for implementing efficient learning protocols. Here, we propose and demonstrate in hardware a spike-driven threshold-based learning rule which goes beyond conventional spike-timing dependent plasticity mechanisms, by also taking into account the neuron membrane potential and its firing rate. The mixed memristive–neuromorphic system we demonstrate comprises an oxide-based memristive synapse device placed between two silicon neurons implemented on a neuromorphic chip that comprises the proper interfacing and spike-based learning circuits designed to drive the memristive elements. We show how the system is able to emulate in real-time weight dependent post-synaptic activity and drive synaptic weight updates at the memristive synapse level following the spike-driven learning rule presented. We validate this spike-based learning mechanism with experimental results and quantify the system performance with basic learning experiments.

Biologically plausible neuromorphic computing systems are attracting considerable attention due to their low latency, massively parallel information processing abilities, and their high energy efficiency. To achieve these features neuromorphic silicon neuron circuits need to be integrated with plastic synapse circuits capable of on-line learning and storage of synaptic weights. Within this context, memristive devices play a key role thanks to their non-volatility, scalability, and compatibility with the complementary metal–oxide–semiconductor fabrication process. However, neuro-memristive systems are still facing difficult challenges for implementing efficient learning protocols. Here, we propose and demonstrate in hardware a spike-driven threshold-based learning rule which goes beyond conventional spike-timing dependent plasticity mechanisms, by also taking into account the neuron membrane potential and its firing rate. The mixed memristive–neuromorphic system we demonstrate comprises an oxide-based memristive synapse device placed between two silicon neurons implemented on a neuromorphic chip that comprises the proper interfacing and spike-based learning circuits designed to drive the memristive elements. We show how the system is able to emulate in real-time weight dependent post-synaptic activity and drive synaptic weight updates at the memristive synapse level following the spike-driven learning rule presented. We validate this spike-based learning mechanism with experimental results and quantify the system performance with basic learning experiments.

Display Omitted An Al:HfO2 memristor emulates the strength change observed in biological synapses.The memristor is self-compliant, so there is no need of external current limitation.A train of identical pulses is applied to the memristor to change its conductance.Pulses with proper voltage-time width gradually change the memristor conductance. Resistive switching devices were at first conceived to be used in memory applications. Recently, they have also been studied as artificial synapses for neuromorphic applications. Therefore, lots of efforts are currently devoted to optimise both materials and programming techniques to design a device able to emulate the behaviour of biological synapses, i.e. able to gradually increase and decrease its conductance when proper electrical signals are applied.In this paper, an Al:HfO2 based memristor is presented as a suitable device as an artificial synapse in future neuromorphic circuits. A train of identical programming pulses was chosen because of its ease of implementation as an efficient and simple programming algorithm to emulate the strength change observed in biological synapses. With this algorithm we demonstrate that the conductance of the device can be both gradually increased and gradually decreased, provided an accurate choice of pulse amplitude and time width is made.

The development of new generation nonvolatile memories, such as Phase Change Memories (PCMs) and Resistive-RAMs (ReRAMs), calls for accurate and controllable programming pulses, which are fundamental to adequately characterize the memory cell. Indeed, the final cell state depends on parameters of the applied programming pulse(s), such as amplitude, duration, and fall time. The performance and the flexibility of conventional automated test equipment (ATE) should be enhanced to carry out reliable tests on different cell implementations, which may have different architectures or material compositions. Aiming at this goal, we designed, fabricated, and experimentally evaluated an on-wafer pulse generator, controlled by commercial ATE, which is able to provide voltage pulses with programmable amplitude, duration, and fall time. A key design requirement was to allocate the generator in the wafer scribe lanes, to reduce the impact of the proposed approach on testing cost. However, this requirement implies that the system must feature reduced silicon area occupation and have a very disadvantageous aspect ratio as well as limited pad count. Since unavoidable process spreads and nonidealities can affect the accuracy of the on-wafer pulse generator, a calibration procedure for pulse parameters was conceived, implemented, and validated. The designed system is able to generate pulses with an amplitude from 0.5 V up to 4.5 V, a pulse duration from 50 ns to 350 ns, and a fall time from 10 ns to several μs (the variability of the last parameter is essential to analyze the response of PCM cells to different quenching times). By using the proposed calibration procedure, it is possible to obtain an accuracy better than ±10% in all the parameters that define the shape of the generated programming pulse. Measurements on a fabricated prototype showed the effectiveness of the presented approach.

In recent years, biologically inspired systems, which emulate the nervous system of living beings, are becoming more and more requested due to their ability to solve ill-posed problems such as pattern recognition or interaction with the external environment. By virtue of their nanoscaled size and their tunable conductance, memristors are key elements to emulate high-density networks of biological synapses that regulate the communication efficacy among neurons and implement learning capability. We propose a TiN/ HfO2/Ti/TiN memristor as artificial synapse for neuromorphic architectures. The device can gradually change its conductance upon application of proper electrical stimuli. More specifically, it features gradual potentiation and depression when stimulated by trains of identical potentiating or depressing spikes, which are easy to be implemented on-chip. Moreover, we demonstrate that the memristor conductance can be regulated according to the delay time between two spikes incoming to the device terminals. This regulation of memristor conductance implements the typical biological learning process named Spike-Time-Dependent-Plasticity (STDP). Finally, collected STDP data were used to simulate a simple fully connected Spiking Neural Network (SNN) for pattern recognition.

The resistance switching dynamics of TiN/HfO2/Pt devices is analyzed in this paper. When biased with a voltage ramp of appropriate polarity, the devices experience SET transitions from high to low resistance states in an abrupt manner, which allows identifying a threshold voltage. However, we find that the stimulation with trains of identical pulses at voltages near the threshold results in a gradual SET transition, whereby the resistive state visits a continuum of intermediate levels as it approaches some low resistance state limit. On the contrary, RESET transitions from low to high resistance states proceed in a gradual way under voltage ramp stimulation, while gradual resistance changes driven by trains of identical spikes cover only a limited resistance window. The results are discussed in terms of the relations among the thermo-electrochemical effects of Joule heating, ion mobility, and resistance change, which provide positive and negative closed loop processes in SET and RESET, respectively. Furthermore, the effect of the competition between opposite tendencies of filament dissolution and formation at opposite metal/HfO2 interfaces is discussed as an additional ingredient affecting the switching dynamics.

The switching dynamics of filamentary Pt/HfO2/TiN memristive devices is managed through sub-threshold pulses in order to display gradual resistance decrease useful for analog logic computation based on spiking networks. Such memristive devices are known to display abrupt set transitions (resistance decrease) that require current limitation because of the triggering of a threshold switching event. In this report, we demonstrate the gradual resistance decrease driven by trains of identical sub-threshold pulses. The experimental finding is explained by a compact model considering a gradual closure of the filament interruption and a following lateral filament growth.

Phase Change Memory (PCM) is the most mature among back-end emerging non-volatile memory concepts. In order to enable embedded PCM applications, the thermal properties of the chalcogenide material have to be boosted, by optimizing its stoichiometry. Ge enrichment of Ge 2 Sb 2 Te 5 (GST) has been proved to be promising for improving the thermal stability of the technology, but also demonstrates an increase of the low-resistance state (LRS) resistivity as well as a larger resistance drift of this state towards higher resistance over time. This phenomenon can be minimized if an appropriate programming voltage pulse is applied, capable of providing a linearly decreasing temperature profile in the active region of the memory device. In this paper, we discuss the LRS resistance increase of PCM cells based on Ge-rich GST and present a programming voltage profile that is capable of generating a linearly decreasing temperature in the memory cell. A circuit that can generate the desired voltage waveform is presented and simulated in order to prove the functionality of the proposed solution.

The study of the behaviour of the cell of emerging memories (such as PCMs and ReRAMs) is fundamental to optimize materials, cell architecture, and programming pulses and algorithms as well as to monitor the actual cell performance. Since the final state of the above memory cells is dependent on the applied programming pulse shape, a buffer able to feed the cell with adequate electrical pulses is needed. In this paper, we propose a buffer targeted at this application, which is able to reproduce fast pulses (time duration of 50 ns and rise and fall times down to 15 ns) and drive up to 2 mW into a 10 kΩ load, while keeping the input-to-output voltage error below 0.4%.

In new and future generations of Non Volatile Memories such as Phase Change Memories (PCMs) and Resistive-RAMs (ReRAMs), having accurate and controllable program pulses is fundamental to adequately characterize the memory cell, since the obtained cell status is a function of the applied pulse parameters. In order to massively test new cells and enhance conventional instrumentation flexibility, an accurate on-chip pulse generator, which is able to provide pulses with different amplitude, falling time, and duration, has been designed, fabricated, and experimentally evaluated. The designed device can generate pulses with amplitude, fall time, and time duration programmable from 0.5 V to 4.5 V, from 10 ns to several μs, and from 50 ns to 350 ns, respectively.