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A new family of scalable codes with locality and availability for information repair in data storage systems for e-health applications was presented recently. The construction was based on a graph of the [7, 3-4] Simplex code. In this paper it is shown that the construction can be generalized via tessellation in a Euclidian plane. The codes obtained have new interesting recoverability properties. They can in some cases repair damage to many storage nodes in multiple connected graphs via sequential decoding, which is similar to healing wounds in biological systems. The advantages of the original codes, namely the availability, functionality, efficiency and high data accessibility, will be preserved also in these new codes. The computational complexity and communication costs of their incrementation will remain constant and modest. These codes could be adapted to disaster recovery because it is straightforward to place the nodes so that the graph is easily mapped on a real structure in space. [ABSTRACT FROM AUTHOR]

The bose-chaudhuri-hocquenghem (BCH) codes are a cyclic error correction codes (ECC) class. The BCH is constructed by using a polynomial over the Galois field. The BCH codes can detect and correct the multi-bits with an easy decoding mechanism. The BCH codes are used in most of the storage device's cryptography, disk drives, and satellite applications. This manuscript presents an efficient high-throughput BCH module with an encoding and decoding mechanism for multi-bit corrections. The BCH code of (15, k) is used to construct the encoder and decoder architectures. The BCH encoder decoder (ED) module with single error correction (SEC), double error correction (DEC), and triple-error correction (TEC) are discussed in detail. The BCH encoder module uses a linear feedback shift register (LFSR). The BCH decoder with SEC and DEC is constructed using the syndrome generator module (SGM) and chien search module (CSM). The BCH decoder with TEC is designed using SGM, inversion-based berlekamp-massey-algorithm (BMA), and CSMs. The BCH-ED module with SEC, DEC, and TEC utilizes <1 % chip area on Artix-7 FPGA. The BCH-ED with SEC, DEC, and TEC achieves a throughput of 7.13 Gbps, 1.2 Gbps, and 0.803 Gbps, respectively. Lastly, the BCH module is compared with existing BCH approaches with better improvement in chip area, frequency, and throughput parameters. [ABSTRACT FROM AUTHOR]

The error performance of the 5G low‐density parity‐check codes is significantly impacted by the update order of layers. At present, the row degree (RD) and the number of punctured bits (PBs) are widely used to decide the update order of layers. Here, the authors propose a metric to assess the soft message recovery speed of coded bits and then suggest updating layers with the lowest RD first rather than those with the least PBs first. Besides, a new criterion is introduced to further determine the update order of layers with the same number of PBs and the same RD. The resulting reordered layered schedule yields better error performance and faster convergence speed than the prior arts. [ABSTRACT FROM AUTHOR]

Abstract Turbo product codes (TPCs) have been widely used for bit error correction in high‐speed applications such as data storage. This letter introduces an efficient hard‐input hard‐output iterating TPC decoder module. A transpose memory utilizing static random access memory (SRAM) is integrated into the decoder to achieve a low hardware overhead. The transpose memory, based on an 8T SRAM bit‐cell, supports both horizontal (row‐wise), and vertical (column‐wise) read/write operations. It is prototyped under a 28nm high‐k/metal gate stack process with bit‐cell size of 0.582 µm2. This specialized SRAM significantly reduces the hardware overhead when compared with a register‐array‐based transpose memory without significant throughput loss. A field programmable gate array (FPGA) evaluation platform is utilized to emulate the TPC decoder module, and the maximum decoder throughput is up to 6.49 Gbps at 250 MHz.

Turbo product codes (TPCs) have been widely used for bit error correction in high‐speed applications such as data storage. This letter introduces an efficient hard‐input hard‐output iterating TPC decoder module. A transpose memory utilizing static random access memory (SRAM) is integrated into the decoder to achieve a low hardware overhead. The transpose memory, based on an 8T SRAM bit‐cell, supports both horizontal (row‐wise), and vertical (column‐wise) read/write operations. It is prototyped under a 28nm high‐k/metal gate stack process with bit‐cell size of 0.582 µm2. This specialized SRAM significantly reduces the hardware overhead when compared with a register‐array‐based transpose memory without significant throughput loss. A field programmable gate array (FPGA) evaluation platform is utilized to emulate the TPC decoder module, and the maximum decoder throughput is up to 6.49 Gbps at 250 MHz. [ABSTRACT FROM AUTHOR]

Channel coding plays a pivotal role in ensuring reliable communication over wireless channels. With the growing need for ultra-reliable communication in emerging wireless use cases, the significance of channel coding has amplified. Furthermore, minimizing decoding latency is crucial for critical-mission applications, while optimizing energy efficiency is paramount for mobile and the Internet of Things (IoT) communications. As the fifth generation (5G) of mobile communications is currently in operation and 5G-advanced is on the horizon, the objective of this paper is to assess prominent channel coding schemes in the context of recent advancements and the anticipated requirements for the sixth generation (6G). In this paper, after considering the potential impact of channel coding on key performance indicators (KPIs) of wireless networks, we review the evolution of mobile communication standards and the organizations involved in the standardization, from the first generation (1G) to the current 5G, highlighting the technologies integral to achieving targeted KPIs such as reliability, data rate, latency, energy efficiency, spectral efficiency, connection density, and traffic capacity. Following this, we delve into the anticipated requirements for potential use cases in 6G. The subsequent sections of the paper focus on a comprehensive review of three primary coding schemes utilized in past generations and their recent advancements: low-density parity-check (LDPC) codes, turbo codes (including convolutional codes), and polar codes (alongside Reed-Muller codes). Additionally, we examine alternative coding schemes like Fountain codes (also known as rate-less codes), sparse regression codes, among others. Our evaluation includes a comparative analysis of error correction performance and the performance of hardware implementation for these coding schemes, providing insights into their potential and suitability for the upcoming 6G era. Lastly, we will briefly explore considerations such as higher-order modulations and waveform design, examining their contributions to enhancing key performance indicators in conjunction with channel coding schemes.

This letter proposes an augmented scheme of LT codes to improve the decoding success rate. The method involves substituting the 1‐s in full‐degree columns of the generator matrix of conventional LT codes with binary extension field elements and simultaneously increasing the ratio of full‐degree columns in the ideal soliton distribution. For non‐full‐degree columns, we retain the nonzero elements as 1‐s in the conventional LT codes generator matrix to preserve computational efficiency. Compared to conventional LT codes, the proposed method enhances the linear independence of the generator matrix, leading to a higher decoding success rate with minimal data packets. Experimental results demonstrate the effectiveness of the method at improving the performance of LT codes, with close to 100% decoding success rate achieved with around 5% data redundancy. [ABSTRACT FROM AUTHOR]

Among numerous dynamic scheduling strategies for low‐density parity‐check codes, many of them are of high complexity due to repetitive computation and ordering of belief residuals. To address these challenges, two novel approaches are proposed: the derived informed variable‐to‐check residual belief propagation and the derived variable‐node and variable‐to‐check‐edge residual belief propagation for low‐density parity‐check codes. Simulation results show that the derived dynamic scheduling exhibits a substantial gain of approximately 0.15 dB in signal‐to‐noise ratio over the non‐derived one with considerably lower decoding complexity when targeting a bit‐error rate of 10−4. [ABSTRACT FROM AUTHOR]

M. Fossorier proposed how to determine the necessary and sufficient conditions for the existence of cycles in the Tanner graph of quasi‐cyclic LDPC (QC‐LDPC) codes, which has been widely investigated in the study of LDPC codes. This paper presents some new necessary and sufficient conditions for the existence of cycles with arbitrary lengths and proposes a simple and novel method for counting cycles of QC‐LDPC codes based on the improved conditions. Numerical results show that, compared with the existing methods, the presented method is effective and feasible and can enumerate cycles of QC‐LDPC codes in a cyclic‐shift way. [ABSTRACT FROM AUTHOR]

Quantum computers have the potential to provide exponential speedups over their classical counterparts. Quantum principles are being applied to fields such as communications, information processing, and artificial intelligence to achieve quantum advantage. However, quantum bits are extremely noisy and prone to decoherence. Thus, keeping the qubits error free is extremely important toward reliable quantum computing. Quantum error correcting codes have been studied for several decades and methods have been proposed to import classical error correcting codes to the quantum domain. Along with the exploration into novel and more efficient quantum error correction codes, it is also essential to design circuits for practical realization of these codes. This article serves as a tutorial on designing and simulating quantum encoder and decoder circuits for stabilizer codes. We first describe Shor’s 9-qubit code which was the first quantum error correcting code. We discuss the stabilizer formalism along with the design of encoding and decoding circuits for stabilizer codes such as the five-qubit code and Steane code. We also design nearest neighbor compliant circuits for the above codes. The circuits were simulated and verified using IBM Qiskit. [ABSTRACT FROM AUTHOR]

Abstract The error performance of the 5G low‐density parity‐check codes is significantly impacted by the update order of layers. At present, the row degree (RD) and the number of punctured bits (PBs) are widely used to decide the update order of layers. Here, the authors propose a metric to assess the soft message recovery speed of coded bits and then suggest updating layers with the lowest RD first rather than those with the least PBs first. Besides, a new criterion is introduced to further determine the update order of layers with the same number of PBs and the same RD. The resulting reordered layered schedule yields better error performance and faster convergence speed than the prior arts.

Fifth-Generation (5G) New Radio (NR) relies on distinct channel interleavers for data and control channels to effectively mitigate burst errors. However, implementing these interleavers individually leads to a substantial increase in silicon cost. To address this challenge and optimize resource utilization while enhancing system performance, a novel Resource Sharing Channel Interleaver (RSCI) architecture for data and control channels in 5G NR is proposed. The RSCI is built upon a straightforward algorithm based on the 3rd Generation Partnership Project (3GPP) Release 15 (R15) standard for 5G NR and is implemented using Xilinx design suite on the Virtex 7 (XC7VX330T) Field Programmable Gate Array (FPGA). The presented RSCI demonstrates remarkable improvements over existing architectures. Specifically, it achieves a reduction in resource utilization by 20% and a cutback in power consumption by 19.2% compared to the existing architecture. To highlight the cost-effectiveness of the proposed approach, both interleavers are implemented as separate entities. Synthesis results indicate that the separate implementation occupies nearly double the resources compared to the combined interleaver implementation.

In this letter, a novel single parity check‐aided minimum sum (SPC‐aided MS) algorithm is proposed. A cascaded compiled code scheme is used to approximate the adaptive belief propagation (ABP) algorithm for Reed–Solomon (RS) codes using the min sum (MS) algorithm. The computational complexity is greatly reduced compared with the previous algorithm. Simulation results show that the SPC‐aided MS algorithm can achieve coding gains of up to 1.1, 0.7, and 0.6 dB for RS (255,239) code compared with the conventional ABP, LRBP, and HD‐P‐ABP algorithms, respectively under the condition of FER=10−3$\text{FER}=10^{-3}$. [ABSTRACT FROM AUTHOR]

The user datagram protocol is the most widely used protocol for streaming multimedia data over the Internet. Like other protocols at the network and transport layers, it uses the Internet Checksum (IC) to detect channel errors. The consequence of this is that each corrupted packet is dropped, which can degrade the quality of service perceived by a user. In this paper, the authors present a solution to this problem based on integer codes capable of correcting single and double adjacent errors. The presented codes are a generalization of the IC, which makes them easy to implement in software. [ABSTRACT FROM AUTHOR]

Quantum key distribution (QKD) can provide information-theoretically secure keys for two parties of legitimate communication, and information reconciliation, as an indispensable component of QKD systems, can correct errors present in raw keys based on error-correcting codes. In this paper, we first describe the basic knowledge of information reconciliation and its impact on continuous variable QKD. Then we introduce the information schemes and the corresponding error correction codes employed. Next, we introduce the rate-compatible codes, the hardware acceleration of the reconciliation algorithm, the research progress of information reconciliation, and its application in continuous variable QKD. Finally, we discuss the future challenges and conclude. [ABSTRACT FROM AUTHOR]

Abstract Among numerous dynamic scheduling strategies for low‐density parity‐check codes, many of them are of high complexity due to repetitive computation and ordering of belief residuals. To address these challenges, two novel approaches are proposed: the derived informed variable‐to‐check residual belief propagation and the derived variable‐node and variable‐to‐check‐edge residual belief propagation for low‐density parity‐check codes. Simulation results show that the derived dynamic scheduling exhibits a substantial gain of approximately 0.15 dB in signal‐to‐noise ratio over the non‐derived one with considerably lower decoding complexity when targeting a bit‐error rate of 10−4.

Abstract In this letter, a novel single parity check‐aided minimum sum (SPC‐aided MS) algorithm is proposed. A cascaded compiled code scheme is used to approximate the adaptive belief propagation (ABP) algorithm for Reed–Solomon (RS) codes using the min sum (MS) algorithm. The computational complexity is greatly reduced compared with the previous algorithm. Simulation results show that the SPC‐aided MS algorithm can achieve coding gains of up to 1.1, 0.7, and 0.6 dB for RS (255,239) code compared with the conventional ABP, LRBP, and HD‐P‐ABP algorithms, respectively under the condition of FER=10−3.

In recent days, an extensive digital communication process has been performed. Due to this phenomenon, proper maintenance of communication encoding and decoding parallel operation without any overhead such as signal attenuation code rate fluctuations during the digital parallel communication process can be minimized and optimized by adopting parallel encoder and decoder operations. To overcome the above-mentioned drawbacks by using proposed reconfigurable code rate cooperative (RCRC) using low-density parity check (LDPC) code for for Gigabits Wide Code Encoder/Décoder Operations. The proposed RCRC is capable to vary the switch parallel operation as per the load. The lowdensity parity check (LDPC) is used for linear error correcting code in the communication process. it is very essential to reduce the power dissipation and noise in a transmission channel. Due to these phenomena, the decrease in power dissipation and enhancement of the accuracy in communication process are achieved and also operate over gigabits/sec data and it effectively performs linear encoding, dual diagonal form, widens the range of code rate and optimal degree distribution of LDPC mother code and all daughter codes for effectively performing the parallel switching operations in highly complex and wide range of code rate communication process. It is the highest upper bounded code rate as compared to the existing methods. The proposed method optimizes the transmission rate and is capable to operate on a 0.98 code rate. It is the highest upper bounded code rate as compared to the existing methods. the proposed method's implementation has been carried out using MATLAB and as per the simulation result, the proposed method is capable of reaching a throughput efficiency greater than 8.2 Gigabits per second with a clock frequency of 160MHz. [ABSTRACT FROM AUTHOR]

Abstract The user datagram protocol is the most widely used protocol for streaming multimedia data over the Internet. Like other protocols at the network and transport layers, it uses the Internet Checksum (IC) to detect channel errors. The consequence of this is that each corrupted packet is dropped, which can degrade the quality of service perceived by a user. In this paper, the authors present a solution to this problem based on integer codes capable of correcting single and double adjacent errors. The presented codes are a generalization of the IC, which makes them easy to implement in software.

In this paper, some affine and rational functions are applied to define a class of LDPC codes, called RLDPC codes, which can be classified in two types, type-I and type-II, depending on being equivalent or not with APM-LDPC codes, respectively. Then, for each type, some explicit methods are provided to generate RLDPC codes with girth at least 6. While, cyclotomic cosets are used to generate type-I RLDPC codes, normal and diameter RLDPC codes are proposed as a class of type-II RLDPC codes which are analyzed for the existence of 4-cycles. Finally, simulation results show that the constructed type-II RLDPC codes outperform the randomly constructed QC LDPC codes, APM-LDPC codes and the LDPC codes based on PEG. [ABSTRACT FROM AUTHOR]

This study endeavors to investigate the effectiveness of machine learning-based methodologies in enhancing the performance and reliability of Power Line Communication (PLC) systems. PLC systems constitute a critical component within the domains of energy management, monitoring, and automation. The fundamental objective herein is to contribute significantly to the scholarly discourse by conducting a comprehensive review encompassing research investigations and practical applications documented in the extant literature. The primary motivation underpinning this research is predicated upon the necessity for a meticulous evaluation of machine learning techniques that hold the potential to enhance the efficacy and stability of PLC systems. The deployment of these techniques bears the promise of engendering heightened levels of efficiency across the spectrum of energy management, communication, and automation systems. Within this scholarly quest, the study posits a hypothesis: Machine learning-based methodologies possess the capacity to effect marked improvements in the performance and reliability of PLC systems. Methodological scrutiny is executed through a comprehensive evaluation of diverse machine learning techniques, including, but not limited to, deep learning, support vector machines, and random forests, facilitated by a series of empirical experiments and simulations. Empirical findings resoundingly corroborate the proposition, substantiating a significant enhancement in the operational performance of PLC systems when these machine learning methods are judiciously employed. In summation, this study assumes the role of a catalyst in exploring latent, untapped potential inherent within machine learning-based methodologies, customarily calibrated to resonate within the intricate matrix of PLC systems. The zenith of this rigorous investigation stands poised to illuminate the path toward transformative advancements in the domains of energy management, communication, monitoring, and automation systems. The findings contribute significantly to the academic discourse, offering a compass for future research inquiries and practical applications within this burgeoning and dynamic field.

DNA has been pursued as a novel biomaterial for digital data storage. While large‐scale data storage and random access have been achieved in DNA oligonucleotide pools, repeated data accessing requires constant data replenishment, and these implementations are confined in professional facilities. Here, a mobile data storage system in the genome of the extremophile Halomonas bluephagenesis, which enables dual‐mode storage, dynamic data maintenance, rapid readout, and robust recovery. The system relies on two key components: A versatile genetic toolbox for the integration of 10–100 kb scale synthetic DNA into H. bluephagenesis genome and an efficient error correction coding scheme targeting noisy nanopore sequencing reads. The storage and repeated retrieval of 5 KB data under non‐laboratory conditions are demonstrated. The work highlights the potential of DNA data storage in domestic and field scenarios, and expands its application domain from archival data to frequently accessed data. [ABSTRACT FROM AUTHOR]

The explosive growth of connected devices demands high quality and reliability in data transmission and storage. Error correction codes (ECCs) contribute to this in ways that are not very apparent to the end user, yet indispensable and effective at the most basic level of transmission. This paper presents an investigation of the performance and analysis of two decoders that are based on hash techniques and syndrome calculation over a Rayleigh channel. These decoders under study consist of two main features: a reduced complexity compared to other competitors and good error correction performance over an additive white gaussian noise (AWGN) channel. When applied to decode some linear block codes such as Bose, Ray-Chaudhuri, and Hocquenghem (BCH) and quadratic residue (QR) codes over a Rayleigh channel, the experiment and comparison results of these decoders have shown their efficiency in terms of guaranteed performance measured in bit error rate (BER). For example, the coding gain obtained by syndrome decoding and hash techniques (SDHT) when it is applied to decode BCH (31, 11, 11) equals 34.5 dB, i.e., a reduction rate of 75% compared to the case where the exchange is carried out without coding and decoding process. [ABSTRACT FROM AUTHOR]

One of the most challenging parts of integrating biometrics and cryptography is the intra variation in acquired identifiers between the same users. Due to noise in the environment or different devices, features of the iris may differ when it is acquired at different time periods. This research focuses on improving the performance of iris biometric authentication and encrypting the binary code generated from the acquired identifiers. The proposed biometric authentication system incorporates the concepts of non-repudiation and privacy. These concepts are critical to the success of a biometric authentication system. Iris was chosen as the biometric identifier due to its characteristics of high accuracy and the permanent presence throughout an individual’s lifetime. This study seeks to find a method of reducing the noise and error associated with the nature of dissimilarity acquired by each biometric acquisition. In our method, we used Reed Solomon error-correction codes to reduce dissimilarities and noise in iris data. The code is a block-based error correcting code that can be easily decoded and has excellent burst correction capabilities. Two different distance metric measurement functions were used to measure the accuracy of the iris pattern matching identification process, which are Hamming distance and weighted Euclidean distance. The experiments were conducted with the CASIA 1.0 iris database. The results showed that the False Acceptance Rate is 0%, the False Rejection Rate is 1.54%, and the Total Success Rate is 98.46%. The proposed approach appears to be more secure, as it is able to provide a low rate of false rejections and false acceptances.

Abstract DNA has been pursued as a novel biomaterial for digital data storage. While large‐scale data storage and random access have been achieved in DNA oligonucleotide pools, repeated data accessing requires constant data replenishment, and these implementations are confined in professional facilities. Here, a mobile data storage system in the genome of the extremophile Halomonas bluephagenesis, which enables dual‐mode storage, dynamic data maintenance, rapid readout, and robust recovery. The system relies on two key components: A versatile genetic toolbox for the integration of 10–100 kb scale synthetic DNA into H. bluephagenesis genome and an efficient error correction coding scheme targeting noisy nanopore sequencing reads. The storage and repeated retrieval of 5 KB data under non‐laboratory conditions are demonstrated. The work highlights the potential of DNA data storage in domestic and field scenarios, and expands its application domain from archival data to frequently accessed data.

We study the list decodability of different ensembles of codes over the real alphabet under the assumption of an omniscient adversary. It is a well-known result that when the source and the adversary have power constraints $P $ and $N $ respectively, the list decoding capacity is equal to $\frac {1}{2}\log \frac {P}{N}$. Random spherical codes achieve constant list sizes, and the goal of the present paper is to obtain a better understanding of the smallest achievable list size as a function of the gap to capacity. We show a reduction from arbitrary codes to spherical codes, and derive a lower bound on the list size of typical random spherical codes. We also give an upper bound on the list size achievable using nested Construction-A lattices and infinite Construction-A lattices. We then define and study a class of infinite constellations that generalize Construction-A lattices and prove upper and lower bounds for the same. Other goodness properties such as packing goodness and AWGN goodness of infinite constellations are proved along the way. Finally, we consider random lattices sampled from the Haar distribution and show that if a certain conjecture that originates in analytic number theory is true, then the list size grows as a polynomial function of the gap-to-capacity. [ABSTRACT FROM AUTHOR]

As the storage density of 3-D NAND flash memory increases, reliability issues become a bottleneck. Among all reliability issues, decreased retention time is the dominant one. To extend the retention time, data refresh is a straightforward approach. However, refresh operations introduce redundant operations, which hurt the performance of the 3-D NAND flash system. With the observation that retention time can be extended by wordline (WL) interference, this letter first proposes to extend retention time with WL interference practically, and then presents a refresh scheme, which refreshes only one-third of pages in a block and postpones the refresh on the remaining two-thirds of pages with WI. The evaluation results show that the refresh operations are reduced by 40.7% at most. Compared with previous work, the read and write response times are decreased by 31.2% and 43.5%, respectively, with a 7-day refresh period. [ABSTRACT FROM AUTHOR]

3-D NAND flash memory with vertically stacked layers has been widely applied benefiting from its large capacities and high performances. Recently, a novel open block operation scheme was proposed for further improvements of the utilization efficiency in large capacity blocks. In this article, reliability issues of the open block operation in 3-D charge-trap (CT) NAND flash memory are studied by focusing on the high raw bit error rates (RBERs) in the last programmed word-line (WL), which is named as the edge WL (EWL). By systematical characterizations, it is concluded that high RBER in the EWL originates from lateral charge migration (LCM) due to the special structure of 3-D CT NAND flash. To suppress the RBER in EWL, we propose the extra read (ER) and extra program (EP) schemes to compensate for the charge loss from LCM. The experimental results show that the RBER of EWL can be reduced by an average of 59.8% and 86.5% after adopting ER and EP schemes, respectively. Furthermore, for the highly reliable open block, we design a targeted low-density parity-check (LDPC) operation process to enhance the correction capability. By using these two methods, experimental results show that the error correction capabilities of the LDPC hard decoding are increased by 1.92 and 4.76 times, respectively. [ABSTRACT FROM AUTHOR]

$\mathbb {Z}_{2^{s}}$ -additive codes are subgroups of $\mathbb {Z}^{n}_{2^{s}}$ , and can be seen as a generalization of linear codes over $\mathbb {Z}_{2}$ and $\mathbb {Z}_{4}$. A $\mathbb {Z}_{2^{s}}$ -linear code is a binary code (not necessarily linear) which is the Gray map image of a $\mathbb {Z}_{2^{s}}$ -additive code. We consider $\mathbb {Z}_{2^{s}}$ -additive simplex codes of type $\alpha $ and $\beta $ , which are a generalization over $\mathbb {Z}_{2^{s}}$ of the binary simplex codes. These codes are related to the $\mathbb {Z}_{2^{s}}$ -additive Hadamard codes. In this paper, we use this relationship to find a linear subcode of the corresponding $\mathbb {Z}_{2^{s}}$ -linear codes, called kernel, and a representation of these codes as cosets of this kernel. In particular, this also gives the linearity of these codes. Similarly, $\mathbb {Z}_{2^{s}}$ -additive MacDonald codes are defined for $s>2$ , and equivalent results are obtained. [ABSTRACT FROM AUTHOR]

Motivated by DNA storage in living organisms, and by known biological mutation processes, we study the reverse-complement string-duplication system. We fully classify the conditions under which the system has full expressiveness, for all alphabets and all fixed duplication lengths. We then focus on binary systems with duplication length 2 and prove that they have full capacity, yet surprisingly, have zero entropy-rate. Finally, by using binary single burst-insertion correcting codes, we construct codes that correct a single reverse-complement duplication of odd length, over any alphabet. The redundancy (in bits) of the constructed code does not depend on the alphabet size. [ABSTRACT FROM AUTHOR]

The lifetime of NAND flash cells significantly degrades with feature-size reductions and multilevel cell technology. On the other hand, we have more and more approximate data, such as images and videos that are more error tolerant than regular data like text. In this article, we propose Rebirth-FTL, which reuses faulty blocks that contain uncorrectable errors to store approximate data for lifetime optimization. Rebirth-FTL effectively manages two spaces, namely, the approximate space and the normal space, with an efficient address translator, a coordinated garbage collection, and a differential wear leveler. In addition, we develop an migration times restriction (MTR) policy to restrict the movement of the approximate data in the approximate space. We also develop a scheme to pass approximate information from userland to kernel space in Linux. Finally, a lifetime model is presented for lifetime analysis. Our experimental results show that Rebirth-FTL can extend the lifetime by 41.63% on average. [ABSTRACT FROM AUTHOR]

Distance-bounding (DB) protocols are used to verify the physical proximity of two devices. DB can be used to establish trusted ad-hoc connections in the industrial Internet-of-Things, e.g., nodes can verify they are deployed in the same location and monitoring the same piece of equipment. Thresholds and error correction codes (ECCs) are two methods to provide error-resilience for DB protocols working in noisy environments. However, the threshold method adds overheads and the ECC method increases the adversary success probability, compared to threshold, when implemented in precommitment DB protocols. In this article, we investigate the ECC method and demonstrate that designers can mitigate increased adversary success probability by using nonsystematic codes. To demonstrate this idea, we compare a prominent precommitment protocol by Brands and Chaum (BC) integrated with different types of ECCs with two existing error-resilience methods, showing how nonsystematic codes provide improved protocol security. Moreover, We further evaluate the BC protocol with nonsystematic ECCs and discuss how to configure protocols to minimize the protocol failure rate, while maintaining adequate attack success probability. [ABSTRACT FROM AUTHOR]

A novel method of spectral decoding for systematic BCH codes has been proposed. This method has a simple description and a small computational complexity.

In real-time video streaming, data packets are transported over the network from a transmitter to a receiver. The quality of the received video fluctuates as the network conditions change, and it can degrade substantially when there is considerable packet loss. Forward error correction (FEC) techniques can be used to recover lost packets by incorporating redundant data. Conventional FEC schemes do not work well when scalable video coding (SVC) is adopted. In this paper, we propose a novel FEC scheme that overcomes the drawbacks of these schemes by considering the reference picture structure of SVC and weighting the reference pictures more when FEC redundancy is applied. The experimental results show that the proposed FEC scheme outperforms conventional FEC schemes.

Finite State Machine (FSM) is widely used in electronic systems and its reliability is critical to the system. Ionizing radiation induced soft error is one of the major concerns in the design of electronic systems, especially in avionics or space applications. Nowadays, the majority of electronic systems relies on single-error correction, double-error detection (SEC-DED) codes to mitigate soft errors. However, the presence of multiple bit upsets is becoming more prevalent as CMOS technology scales down. In addition, state registers in FSMs usually have variable bit-widths and have strict requirement on encoding and decoding delay, which poses challenges for error mitigation techniques. This paper presents an Error Detection and Correction (EDAC) code for state register protection, which can achieve single-error correction, double-error correction and triple-adjacent-error correction (SEC-DEC-TAEC) ability. The proposed code can be used to protect data with $4n$ bit-width ( $n=2,3,4,\ldots $ ) using one common encoder and decoder code block and introduces minimal delay. Experiment results show that the proposed code has better error correction ability than most existing MCU correction codes. Besides, it reduces area occupation by 30% and delay by 15% compared with Orthogonal Latin Square (OLS) code in the case of 8 bit-width data.

As the feature size of transistors decreases, multiple bit upsets and single event transient effects become severe in circuits working in radiation environment. In static random-access memories (SRAM), both single event upsets and single event transients need caring about. Fault-tolerant ECCs are optional for SRAM protection, which own the ability to deal with SEU and SET at the same time. We designed a series of low complexity burst error correcting codes with fault detection feature. This can deal with burst errors in memories and transient errors in the decoder. Low complexity ECC simplifies the decoding circuits and reduces hardware overhead. Compared with schemes to deal with SET in decoders, the proposed scheme has obvious advantage on area's overhead and can be an effective choice for SRAM protection in radiation environment. • A series of low complexity error correction codes (ECC) are designed to fit the requirements on column vectors. • Concurrent Error Detection is implemented in the ECC to realize SET protection of decoders. • Proposed schemes can protect codec from SET with a lower overhead than fault-secure ECC and TMR. The latency is 30% lower and the area is 20% lower than the other schemes. [ABSTRACT FROM AUTHOR]

Abstract A covert channel is a communication channel that is not intended to exist, and that can be used to transfer information in a manner that violates the system security policy. Attackers can abuse such channels to exfiltrate sensitive information from cyber‐physical systems (CPSs), for example to leak the confidential or proprietary parameters in a control system. Furthermore, attacks against CPSs can exploit the leaked information about the implementation of the control system, for example to determine optimal false data injection attack values that degrade the system performance while remaining undetected. In this study, a control theoretic approach for establishing covert channels in stochastic CPSs is presented. In particular, a scenario is considered where an attacker is able to inject malware into the networked controller and arbitrarily alter the control logic. By exploiting such capability, an attacker can establish an illegitimate communication channel, for example to transmit sensitive plant parameters, between the networked controller and an eavesdropper intercepting the sensor measurements. The authors show that such a channel can be established by exploiting the closed‐loop system operations, a decoding mechanism based on an unknown input observer, and an error‐correcting coding scheme that exploits the control loop to obtain an implicit acknowledgement. A simple proof of concept implementation of the covert channel is presented, and its performance is evaluated by resorting to a numerical example. Finally, some defences and countermeasures are proposed against the proposed covert channel.

In recent years, NAND flash memory has been widely used in mobile devices, laptops, desktops, and data center storage systems due to its low-power consumption, high performance, high density, lightweight, shock resistance, and high-reliability natures. However, as the stacked layers and the storage density increase, flash memory also suffers from a higher raw bit error rate (RBER) and shorter lifetime. Observing that reliable cell states suffer from less data retention errors and program disturbance, we propose a differential evolution coding scheme to increase the probability of storing data in more reliable cell states, thereby reducing the RBER. We conducted the experiments over a development platform of SSD storage device with 3D-TLC charge trap (CT) NAND flash memory. The experimental results showed that the proposed differential evolution algorithm with asymmetric coding scheme could averagely reduce RBER by 48.88%, 65.45%, 52.61%, 61.99%, 80.19%, and 33.18% compared with baseline, asymmetric coding algorithm, asymmetric coding scheme with stripe-pattern elimination algorithm, UAC- $n$ LC, word-line batch score modulation programming, and SCB schemes. [ABSTRACT FROM AUTHOR]

We propose a new type of ultimate-Shannon-limit-approaching codes called spatially coupled protograph-based low-density parity-check Hadamard convolutional codes (SC-PLDPCH-CCs), which are constructed by spatially coupling PLDPC-Hadamard block codes. We develop an efficient decoding algorithm that combines pipeline decoding and layered scheduling for the decoding of SC-PLDPCH-CCs, and analyze the latency and complexity of the decoder. To estimate the decoding thresholds of SC-PLDPCH-CCs, we first propose a layered protograph extrinsic information transfer (PEXIT) algorithm to evaluate the thresholds of spatially coupled PLDPC-Hadamard terminated codes (SC-PLDPCH-TDCs) with a moderate coupling length. With the use of the proposed layered PEXIT method, we develop a genetic algorithm to find good SC-PLDPCH-TDCs in a systematic way. Then we extend the coupling length of these SC-PLDPCH-TDCs to form good SC-PLDPCH-CCs. Results show that our constructed SC-PLDPCH-CCs can achieve comparable thresholds to the block code counterparts. Simulations illustrate the superiority of the SC-PLDPCH-CCs over the block code counterparts and other state-of-the-art low-rate codes in terms of error performance. For the rate-0.00295 SC-PLDPCH-CC, a bit error rate of 10−5 is achieved at $E_{b}/N_{0} = -1.465$ dB, which is only 0.125 dB from the ultimate Shannon limit. [ABSTRACT FROM AUTHOR]

Intelligent connected objects, the building blocks of IoT, represent battery supplied electronic devices. These devices are expected to be deployed in very large numbers, and manual replacement of their batteries will severely restrict their large-scale or wide area deployments. Therefore, energy efficiency is of the utmost importance in the design of the IoT devices. The wireless communication between the distributed sensor devices and the host stations can consume significant energy, even more when larger coverage is required. Ultra-low-power wake up radio (WuR) represent one of the most prominent solutions for energy efficiency in IoT. However, the WuR devices have several limitations that bound their practical applicability and usage, such as short range capabilities and low signal sensitivity. As a result, the WuR devices commonly misinterpret their wake up address and inevitably lead to overall performance degradation of the system. This work, introduces the concept of error correction codes in the wake up address. It is envisioned that the error correction codes can increase the overall robustness and sensitivity of the WuR devices. The work also analyses the potential energy efficiency gains and the energy-latency tradeoff degradation of the WuR based IoT system when utilizing the error correction codes. [ABSTRACT FROM AUTHOR]