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The human retina sends visual signals to the brain's visual cortex from photoreceptors (rod and cone cells) through various synaptic pathways and performs crucial early vision processing before signals are passed to higher brain regions. Herein, an artificial retina system implemented based on the leaky integrate‐and‐fire spiking neuron model is presented. The architecture of the proposed retina system consists of a multilayer convolutional neural network (CNN), and the system uses spike timing‐dependent plasticity (STDP) as a feedforward learning rule. In addition, the system integrates a feedback plasticity learning rule to expedite learning convergence. The system weights are implemented using nanoscale memristor arrays, taking on a constrained (radix‐X) range of conductance states. The proposed system produces an output image of 25 × 25 pixels, corresponding to the output retina ganglion cells that act as the interface between the retina and the visual cortex, using an input image of 100 × 100 pixels. [ABSTRACT FROM AUTHOR]

Existing computational models of the retina often compromise between the biophysical accuracy and a hardware-adaptable methodology of implementation. When compared to the current modes of vision restoration, algorithmic models often contain a greater correlation between stimuli and the affected neural network, but lack physical hardware practicality. Thus, if the present processing methods are adapted to complement very-large-scale circuit design techniques, it is anticipated that it will engender a more feasible approach to the physical construction of the artificial retina. The computational model presented in this research serves to provide a fast and accurate predictive model of the retina, a deeper understanding of neural responses to visual stimulation, and an architecture that can realistically be transformed into a hardware device. Traditionally, implicit (or semi-implicit) ordinary differential equations (OES) have been used for optimal speed and accuracy. We present a novel approach that requires the effective integration of different dynamical time scales within a unified framework of neural responses, where the rod, cone, amacrine, bipolar, and ganglion cells correspond to the implemented pathways. Furthermore, we show that adopting numerical integration can both accelerate retinal pathway simulations by more than 50% when compared with traditional ODE solvers in some cases, and prove to be a more realizable solution for the hardware implementation of predictive retinal models. [ABSTRACT FROM AUTHOR]

Memcapacitors (MCs) are promising candidates for the future design of low-power integrated neuromorphic computing systems, with particular emphasis on dynamical spiking neuron models that exhibit rich temporal behaviors. We present a novel floating flux-controlled MC that is designed using only three current feedback amplifiers, one analog multiplier, one capacitor and one resistor. Compared with existing floating MC emulators, our proposed design has a simpler structure without the need for DC biasing voltage sources, and can operate at higher working frequencies, and therefore enabling rapid prototyping of applied MC circuits for experimental verification of large-scale MC arrays. The consistency of the theoretical analysis, simulation and experimental results confirms the correctness and practicability of this new memcapacitor emulator. To further demonstrate a potential use of our MC, in this work, we apply the MC as the first parameterizable leaky integrator for spiking neuron through simulation and experiments. The intrinsic tunable capacitance of the MC can bring about novel short-term memory dynamics to neuronal circuits by dynamically modifying the membrane time constant on-the-fly, which ultimately resembles long-term potentiation, and can thus offer longer term memory. Our results highlight the potential for integrating heterogeneous spiking neural networks with richer temporal dynamics that rely on MC-based circuits to further the capability of neuromorphic computing. [ABSTRACT FROM AUTHOR]

Wireless sensor nodes are heavily resource-constrained due to their edge form factor, which has motivated increasing battery life through low-power techniques. This paper proposes a power management method that leads to less energy consumption in an idle state than conventional power management systems used in wireless sensor nodes. We analyze and benchmark the power consumption between Sleep, Idle, and Run modes. To reduce sensor node power consumption, we develop fine-grained power modes (FGPM) with five states which modulate energy consumption according to the sensor node's communication status. We evaluate the proposed method on a test bench Mica2. As a result, the power consumed is 74.2% lower than that of conventional approaches. The proposed method targets the reduction of power consumption in IoT sensor modules with long sleep mode or short packet data in which most networks operate. [ABSTRACT FROM AUTHOR]

In this paper, a behavioral SPICE memristor model for digital logic implementation is presented and demonstrated in LTSpice. We show binarized state switching and voltage thresholding in the model, which are both important features in practical digital systems. The use of this SPICE model is straightforward and intuitive because almost all parameters in the model can be changed according to the application, including the threshold voltage and the memristance. The LTSpice circuit simulation shows the same characteristics as the original MATLAB numerical implementation, which means that the circuit-level SPICE model can be integrated with other designs. Three types of memristor digital logic circuits are simulated with the LTSpice model with positive results, which proves that the behavioral memristor model has potential application in digital system design. [ABSTRACT FROM AUTHOR]

We develop a tri-state memristive system based on composable binarized memristors, from both a dynamical systems construction to the development of in-house fabricated devices. Firstly, based on the SPICE model of the binary memristor, the series and parallel circuits of binary memristors are designed, and the characteristics of each circuit are analyzed in detail. Secondly, through the analysis of the connection direction and parameters of the two binary memristors, an effective method to construct a tri-state memristor is proposed, and verified using SPICE simulations. Finally, the characteristics of the constructed equivalent tri-state memristor are analyzed, and it is concluded that the amplitude, frequency and type of the input signal can affect the characteristics of the equivalent tri-state memristor. Predictions from this modeling were validated experimentally using Au/ Nb 2 O 5 /Nb cross-point devices. [ABSTRACT FROM AUTHOR]

Fractional-order systems generalize classical differential systems and have empirically shown to achieve fine-grain modeling of the temporal dynamics and frequency responses of certain real-world phenomena. Although the study of integer-order memory element (mem-element) emulators has persisted for several years, the study of fractional-order mem-elements has received little attention. To promote the study of the characteristics and applications of mem-element systems in fractional calculus and memory systems, a novel universal fractional-order mem-elements interface for constructing three types of fractional-order mem-element emulators is proposed in this paper. With the same circuit topology, the floating fractional-order memristor, the fractional-order memcapacitor, and fractional-order meminductor emulators can be implemented by simply combining the impedances of different passive elements. PSPICE circuit simulation and printed circuit board hardware experiments validate the dynamical behaviors and effectiveness of our proposed emulators. In addition, the dynamic relationship between fractional-order parameters and values of fractional-order impedance is explored in MATLAB simulation. The proposed fractional-order mem-element emulators built based on the universal interface are constructed with a small number of active and passive elements, which not only reduces the cost but also promotes the development of fractional-order mem-element emulators and application research for the future. [ABSTRACT FROM AUTHOR]

In large-scale high-density integrated circuits, memristors in close proximity to one another both influence, and are influenced by, the behavior of nearby memristors. However, the previous analyses of memristors-based circuit applications have seldom considered the possibility of coupling effects between memristors which invariably influences the response of all memristors, thus rendering much previous research as incomplete. In this paper, the circuit dynamics of memristive Chua's circuits are systematically analyzed based on a pair of compositely connected flux-controlled memristors characterized by cubic nonlinearity as a typical example. A theoretical analysis is undertaken and verified via MATLAB. While tuning the coupling strength, variations in circuit dynamics are characterized by phase portraits, bifurcation diagrams, and Lyapunov exponents. A new floating memristor emulator with coupling ports, described by cubic nonlinearity, is designed using off-the-shelf circuit devices and is shown to be successfully used in building chaotic circuits in hardware experiments, verifying theoretical results in simulations. This paper provides a new way through which memristors-based circuit dynamics can be influenced by tuning the coupling strength between memristors without changing other circuit parameters. It is further highlighted that when designing future memristors-based circuits, the coupling action between memristors should be considered if necessary and compensated when causing undesired circuit responses. [ABSTRACT FROM AUTHOR]