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Consumer demand for low-power mobile ICs has propelled CMOS scaling to arrive at the fully depleted finFET with foundry offerings already available at 16/14, 10, and 7 nm. The compact three-dimensional structure of the finFET offers superior short-channel control that achieves digital power reduction while increasing device performance for a given area. As system-on-chip technology remains driven by logic and SRAM scaling needs, designers of analog/mixed-signal subsystems must continue to adapt to new technology constraints. We attempt to summarize the challenges and technology considerations encountered when we port analog/mixed-signal designs to a finFET node. At 16/14 nm and beyond, designers also face many implications from scaling innovations leading to the finFET.

The industry's first 10nm low power high performance mobile SoC has been successfully ramped in production. Thanks to a thorough design-technology co-development, 10nm SoC is 16% faster, 37% smaller, and 30% lower power than its 14nm predecessor. The latest SoC features a gigabit class modem and is set to advance AR/VR, AJ, machine learning, and computing. 10nm FinFet technology scaling challenges such as sharply increased wiring resistance and variation and strong layout stress effects are discussed to illustrate design and technology co-development from technology definition to product ramp stage is imperative to realize scaling entitlements.

A cost competitive 20nm technology node is described that enabled industry-first 20nm cellular modem chip with 2× peak data rates vs 28nm, and 2× carrier aggregation. Process and design enhancements for layout context optimization, and continuous process improvements resulted in 18% boost in circuit performance while simultaneously achieving >30% power reduction. 3 mask local interconnect and 64nm double patterning lower level metals - with yield-friendly single color pitch of 95nm and M1 special constructs with 90nm (=gate pitch) single color pitch for cell abutment - were used for achieving ~2× gate density. Single patterning 80nm pitch metal for routing levels was optimized for both density and performance. Active/passive device and double pattern metal mask count was optimized to reach process should-cost goals. Resulting technology provides cost reduction vs 28 HKMG per close to historical trend, and also cost-competitiveness vs 28 PolySiON. Leveraging of yield learning of this common back-end metallization results in up to 6 month pull-in of 16nm Finfet node yield ramp.

Despite improved device performance over traditional Poly-SiON technology, high-K metal gate flow introduces additional device variations not previously seen in Poly-SiON process, especially impacting large dimensional (WxL) devices for matching critical applications. For the first time, we report a comprehensive analysis of device variations introduced from metal gate process, GDIM and GGIM, and their sensitivity to circuit layout. Design optimization and verification mechanisms are developed to mitigate metal gate process induced variations in analog matching circuits. After co-optimization, DAC Vt mismatch is reduced by 2.1X and ADC comparator speed is improved by 23.5% in the analog blocks of an advanced mobile SoC currently in production.

Mobile devices spend most of the time in standby mode. Supported features and functionalities are increasing in each newer model. With the wide spread adaptation of multitasking in mobile devices, retaining current status and data for all active tasks is critical for user satisfaction. Extending battery life in portable mobile devices necessitates the use of minimum possible energy in standby mode while retaining present states for all active tasks. This paper for the first time, explains the low voltage data-retention failure mechanism in flops. It analyzes the impact of design and process parameters on the data retention failure. Statistical nature of data retention failure is established and validated with extensive Monte-Carlo simulations across various process corners. Finally, silicon measurement from several 28nm industrial mobile chips is presented showing good correlation of retention failure prediction from simulation.

Mobile devices spend most of the time in standby mode. Supported features and functionalities are increasing in each newer model. With the wide spread adaptation of multi-tasking in mobile devices, retaining current status and data for all active tasks is critical for user satisfaction. Extending battery life in portable mobile devices necessitates the use of minimum possible energy in standby mode while retaining present states for all active tasks. This paper for the first time, explains the low-voltage data-retention failure mechanism in ops. It analyzes the impact of design and process parameters on the data-retention failure. Statistical nature of data retention failure is established and validated with extensive Monte-Carlo simulations across various process corners. Finally, silicon measurement from several 28nm industrial mobile chips is presented showing good correlation of retention failure prediction from simulation.

We provide two qualitative models for the operation of Josephson fluxon–antifluxon transistor based on the pendulum model and image currents induced in the junction. This device, which is a variant of a Josephson vortex flow transistor, utilizes high temperature superconductor long Josephson junctions with a control line on top of the junction. Our models are consistent with the experimental observation that the coupling efficiency increases with this geometry. We also provide a quantitative model using numerical simulations to confirm the static and dynamic characteristics predicted by the intuitive models.

Embedded memories are widely used in low power System-on-Chip (SoC) applications. Low power performance can be optimized with process, circuits, architecture and system level co-development. In this paper, low power design considerations are described in advanced technology nodes to address memory leakage and active power dissipation. Memory bit cell design in context of process technology definition, circuit techniques at the macro design level, and chip-level integration considerations for low power are described.

With newer technology nodes, circuit/device/process codesign is essential to realize the advantages of scaling. Leveraging co-design approach based on a well-established manufacturing flow, a cost effective 28 nm 4G SOC technology has been crafted. This 28 nm design strategy uses two sets of design rules and 7 different Vt cells with optimal power gating to achieve a 2.4× increase in gate density, 55% decrease in power and 30% gain in frequency with respect to the 45 nm counterpart. Relevant technical tradeoffs between the design/technology interactions are discussed to illustrate the codesign aspects.