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Approximate Computing has recently emerged as a promising solution to enhance circuits performance by relaxing the requisite on exact calculations. Multimedia and Machine Learning constitute a typical example of error resilient, albeit compute-intensive, applications. In this dissertation, the design and optimization of approximate fundamental VLSI digital blocks is investigated. In chapter one the theoretical motivations of Approximate Computing, from the VLSI perspective, are discussed. In chapter two my research activity about approximate adders is reported. In this chapter approximate adders for both traditional non-error tolerant applications and error resilient applications are discussed. In chapter three precision-scalable units are investigated. Real-time precision scalability allows adapting the precision level of the unit with the precision requirements of the applications. In this context my research activities regarding approximate Multiply-and-Accumulate and memory units are described. In chapter four a precision-scalable approximate convolver for computer vision applications is discussed. This is composed of both the approximate Multiply-and-Accumulate and memory units, presented in the chapter three.

Approximate computing is an emerging trend in digital design that trades off the requirement of exact computation for improved speed and power performance. This paper proposes novel approximate compressors and an algorithm to exploit them for the design of efficient approximate multipliers. By using the proposed approach, we have synthesized approximate multipliers for several operand lengths using a 40-nm library. Comparison with previously presented approximated multipliers shows that the proposed circuits provide better power or speed for a target precision. Applications to image filtering and to adaptive least mean squares filtering are also presented in the paper.

The generation of complex signal sources is important for test and validation of electronic systems. With reference to noise sources, commercial systems usually provide white noise sources, while the scientific literature only recently proposed circuits that generate programmable colored noise. This paper proposes a filtering circuit and an algorithm to design the same that produces an arbitrary colored electrical noise. The proposed system improves the performances of the previously proposed circuits in terms of spectral characteristics of the output, in terms of logic resource occupation and power dissipation, while providing no penalty on the working frequency.

A variable latency adder (VLA) reduces average addition time by using speculation: the exact arithmetic function is replaced by an approximated one, that is faster and gives correct results most of the times. When speculation fails, an error detection and correction circuit gives the correct result in the following clock cycle. Previous papers investigate VLAs based on Kogge-Stone, Han-Carlson or carry select topologies, speculating that carry propagation involves only a few consecutive bits. In several applications using 2's complement representation, however, operands have a Gaussian distribution and a nontrivial portion of carry chains can be as long as the adder size. In this paper we propose five novel VLA architectures, based on Brent-Kung, Ladner-Fisher, Sklansky, Hybrid Han-Carlson, and Carry increment parallel-prefix topologies. Moreover, we present a new efficient error detection and correction technique, that makes proposed VLAs suitable for applications using 2's complement representation. In order to investigate VLAs performances, proposed architectures have been synthesized using the UMC 65 nm library, for operand lengths ranging from 32 to 128 bits. Obtained results show that proposed VLAs outperform previous speculative architectures and standard (non-speculative) adders when high-speed is required.

The reduced benefits offered by technology scaling in the nanoscale era call for innovative design approaches, to process bigger and bigger amount of data with always higher performance and lower power consumption. In this respect, Approximate Computing constitutes one of the most promising trend, where efficiency is increased by breaking the dogma of error-free computations, enlarging the design space with the addition of application-specific quality metrics. Approximate Computing paradigm can be applied at different layers, spanning from software to systems and circuits. In this paper we focus on approximate arithmetic circuits for computer vision and machine learning. These kinds of applications have an excellent resiliency to computation errors. Moreover, their arithmetic-intensive processing makes the increase of efficiency of arithmetic circuits a keypoint. In this kind of context Approximate Computing can make the difference, improving, at the same time, performance and power consumption with tolerable quality degradation.

Least-Mean-Square (LMS) is the most popular adaptive filtering algorithm, due to its numerical stability, satisfactory steady-state error and relatively low computational complexity. LMS algorithm is commonly employed in a multitude of tasks such as channel equalization, adaptive noise cancellation, system identification and frequency tracking. Owing to its computational complexity, LMS algorithm is commonly implemented in hardware, in which, due to speed and energy constraints, a fixed-point arithmetic is usually adopted. As shown in the literature, the effects due to fixed-point arithmetic alter the behavior of the algorithm, causing a significant increase in the steady-state error, due to the so-called stall phenomenon. In this paper we propose a novel fixed-point scheme which significantly limits the stalling. This gives increased flexibility to the designer in the choice of the step-size, that controls the tradeoff between convergence rate and steady-state-error. Implementation results in a 40nm CMOS technology are presented in the paper, to assess the impact of the proposed scheme in terms of area, speed and power.

The use of digital pulse-width modulators (DPWMs) as controllers for dc–dc converters is becoming more and more popular, due to the lower sensitivity to process variations, programmability, and easiness to translate complex control algorithm in digital architecture. DPWMs require high resolution to avoid limit cycling. Moreover, especially in high-frequency switching power converters, the reduction of the electromagnetic interference (EMI) is of primary importance. A novel DPWM circuit is proposed in this paper. The circuit uses only standard cells, easing portability to new technological nodes. The DPWM includes a coarse delay stage, based on an enhanced counter-based architecture, which is able to modulate both the frequency and duty cycle. As a result, the proposed DPWM supports spread-spectrum modulation, with arbitrary modulation law, to reduce the EMI. The DPWM also includes a fine delay stage that employs digitally controlled NAND-based delay lines with excellent linearity and resolution. A measurement unit is used to compensate at run time, the process, voltage, and temperature variations. The circuit has been fabricated in low-cost UMC 130-nm CMOS technology and is fit in a 44-pin package. The chip can generate spread-spectrum pulse-width waveforms up to 10 MHz. Measurement of the conducted EMI in buck dc–dc converter is reported in this paper.

Approximate computing relaxes algorithm precision constraints to improve digital circuit performance. Adaptive filters based on least-mean-square (LMS) algorithm constitute a standard in many DSP applications. The LMS algorithm, being an approximation of the Wiener filter, is inherently imprecise, and constitutes a fertile ground to employ approximate hardware techniques with the additional challenge related to the presence of a feedback path for coefficients update. In this paper, approximate LMS adaptive filters are explored for the first time, by employing approximate multipliers. A system identification scenario is adopted to assess the algorithm behavior. The analysis reveals that the choice of the approximate multiplier topology should be carefully examined, otherwise the stability and convergence performance of the algorithm can be compromised. We propose a novel approximate multiplier able to reduce the power dissipation in adaptive LMS filters up to 29% with tolerable convergence error degradation.

Approximate computing improves digital circuit performance by relaxing the requirement of performing exact calculations. In this paper, we investigate the use of approximate adders in the final stage of a carry save multiplier-accumulator (MAC), designed for image filtering application. We propose a design flow based on synthesis tools, starting from HDL description. After a first step in which an exact carry-propagate adder is used, the synthesized netlist is simulated to extract the statistics of the terms summed in the carry-propagate adder. We then design the approximate adder, to meet the required error characteristics given the inputs statistics. The netlist is finally modified by substituting the exact adder with the approximate one, and a final synthesis and optimization is performed. The presented design example in 28nm CMOS shows that a 14% power gain can be obtained, with a limited image quality degradation.

The paper proposes a SISO register circuit, functionally equivalent to a Shift Register, that is the optimal design choice when the input data have a reduced transition probability. The proposed circuit obtains improved performances by only storing the transitions of the input data, thus saving logic and power.

Sacrificing exact calculations to improve digital circuit performance is at the foundation of approximate computing. In this paper, an approximate multiply-and-accumulate (MAC) unit is introduced. The MAC partial product terms are compressed by using simple OR gates as approximate counters; moreover, to further save energy, selected columns of the partial product terms are not formed. A compensation term is introduced in the proposed MAC, to reduce the overall approximation error. A MAC unit, specialized to perform 2D convolution, is designed following the proposed approach and implemented in TSMC 40nm technology in four different configurations. The proposed circuits achieve power savings more than 60%, compared to standard, exact MAC, with tolerable image quality degradation.

Approximate computing leverages the inherent error resiliency present in many applications to improve circuits performance. Precision-scalable systems dynamically introduce approximations to trade off power and quality, based on the application under execution and the incoming dataset. In this paper, this principle is explored for the first time in the context of latch memories by introducing the ability to scale their precision, while retaining the ability to synthesize them in an automated manner. This offers additional opportunities to reduce energy, compared to the well-known suitability for aggressive voltage scaling of latch memories. A case study based on image processing applications is presented to evaluate the quality-power trade-off in 40nm CMOS. The analysis shows that the total power is reduced by up to 56% when the precision requirement is relaxed.

Approximate computing is emerging as a new paradigm to improve digital circuit performance by relaxing the requirement of performing exact calculations. Approximate adders rely on the idea that for uniformly distributed inputs, long carry-propagation chains are rarely activated. Unfortunately, however, the above assumption on input signal statistics is not always verified; in this paper we focus on the case (often encountered in practical signal processing applications) when the inputs have a Gaussian distribution. We show that for Gaussian inputs the error probability of previously proposed approximate adders approaches 25% for low sigma values, which is much larger than the uniform case. On the basis of this analysis, we propose an approximate adder with a correction circuit that drastically reduces the error rate for Gaussian distributed operand s. In order to investigate the performance of our approach in a real application, simulated results for a simple audio processing system are reported. Implementation results in 65nm technology are also presented.

The generation of complex signal sources is important for test and validation of electronic systems. With reference to noise sources, commercial systems only provide white noise sources while the scientific literature only recently proposed circuits that generate programmable colored noise. This paper proposes a programmable colored noise generator that, while generating noise signals with features matching the state of the art, overcomes the previously proposed circuits in terms of speed (+10%) and logic resource occupation (−75%).

Speculation can enhance adders performance by making carry predictions. It consists in replacing the arithmetic function with a faster, approximated, one, giving correct results most of the time. An error detection stage flags the misprediction events, in such cases, a two-cycles error correction stage is used, constituting a variable latency speculative adder. This paper proposes novel variable latency speculative adders based on Han-Carlson parallel-prefix topologies. The proposed adders are more effective than variable latency Kogge-Stone adders previously proposed in literature. A novel error detection technique that reduces error probability, compared to previous approaches, is proposed. Synthesis results, in the UMC 65nm library, show that proposed variable latency topologies outperform previously developed speculative Kogge-Stone adders and non-speculative ones, when high-speed is required. It is also shown that non-speculative adders remain the best choice when the speed constraint is relaxed.

Variable latency adders have been recently proposed in literature. A variable latency adder employs speculation: the exact arithmetic function is replaced with an approximated one that is faster and gives the correct result most of the time, but not always. The approximated adder is augmented with an error detection network that asserts an error signal when speculation fails. Speculative variable latency adders have attracted strong interest thanks to their capability to reduce average delay compared to traditional architectures. This paper proposes a novel variable latency speculative adder based on Han-Carlson parallel-prefix topology that resulted more effective than variable latency Kogge-Stone topology. The paper describes the stages in which variable latency speculative prefix adders can be subdivided and presents a novel error detection network that reduces error probability compared to previous approaches. Several variable latency speculative adders, for various operand lengths, using both Han-Carlson and Kogge-Stone topology, have been synthesized using the UMC 65 nm library. Obtained results show that proposed variable latency Han-Carlson adder outperforms both previously proposed speculative Kogge-Stone architectures and non-speculative adders, when high-speed is required. It is also shown that non-speculative adders remain the best choice when the speed constraint is relaxed.