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A digital circuit can be viewed as a network of transistors switching between low and high voltages. These transistors and the wires interconnecting them cause delays in signal propagation. In most cases, designers aim to minimize the delays in order to increase processing speed. Nevertheless, some applications such as delay lines, time to digital converters, asynchronous logic and others require the ability to precisely control a delay between two points in a circuit. This paper proposes a novel way to control the delays in an FPGA by dynamically configuring the routing matrices to build a path with the required delay and to calibrate the delays. Such low-level configuration is possible with a dynamic reconfiguration library we developed for Xilinx FPGAs. Our experiments on Virtex-II Pro devices show that any differential delay in a range of 947 ps can be reached with a precision of +/- 18 ps.

Xilinx VirtexII Pro FPGAs support dynamic reconfiguration. To benefit from this functionality, Xilinx proposes a modular and differential development flow, which consists in precompiling all possible configurations and switching from one to another in real time. The pre-compilation process is too slow and static. Xilinx also supplies JBits, but this tool does not support the VirtexII Pro FPGA and later devices. We aim to dynamically produce digital circuits. Unfortunately, since Xilinx does not entirely document the format of the FPGA bitstreams, it is in principle impossible to produce bitstreams without using their tools. This paper presents the methodology we have used to determine the Xilinx bitstream format in order to quickly produce valid configurations on the fly using only our tools. Our synthesis approach translates a simple expression language into a dataflow graph of predefined tiles which are placed and interconnected using the bitstream format information we gathered.

John von Neumann proposed his famous architecture in a context where hardware was very expensive and bulky. His goal was to maximize functionality with minimal hardware. Presently, logical gates are nearly free and single chips contain billions of gates. However, most current designs are still based on Von Neumann's architecture because processors are built on this model. Nevertheless, the main current challenge is to be able to design, refine, synthesize and verify new architectures in a minimum time and with a maximum computational performance regardless of the gate count. Data driven architectures enable a high level of parallelism because instead of a single controller managing all the resources (and often a single ALU), tens or hundreds of small controllers can now operate in parallel on local processing units. This paper presents an environment for the high level description, refinement, synthesis and verification of such systems. Our own HDL is presented with its compiler and we show how it can be used as the intermediate language of a compiler for an even higher level functional programming language. Ongoing work enables the interfacing with other languages (from both hardware and software communities). We also intend to target asynchronous designs.