Search

Conductance DLTS measurements have been performed on 4H-SiC MESFETs. A broad band due to electron emission by different levels is observed. An additional “hole-like” level with activation energy of 0.9 eV is obtained in linear regime but not in saturation regime. From the results, it is proposed that this “hole-like” signal is due to capture of electron present at a conductive SiC/SiO2 interfacial layer.

In this paper we present static measurements fand defects analysis performed on 4H-SiC MESFETs on semi-insulating (SI) substrates containing vanadium. I d-Vds -T and I d-Vgs -T characteristics show anomalies (Threshold voltage shift, leakage current, degradation in saturation current...). Deep defects analysis performed by capacitive transient spectroscopy (C-DLTS) proves the presence of one deep defect called E1 with an activation energy 0.32eV. The studies of C-DLTS signal with pulse duration (t p) and polarization voltage (V r) confirm that E 1 trap is a point defect. Current transient spectroscopy (I-DLTS) performed in the same devices confirm E1 defect and shows the presence of six levels with activation energies ranging from 0.09eV to 1.01eV. The localization and the identification of these defects is presented. Finally, the correlation between the anomalies observed on output characteristics and defects is discussed.

This work deals with the performances of two electrical techniques to characterize deep levels in HEMTs. Capacitance Deep Level Transient Spectroscopy (DLTS) is a well-known method and its efficiency is now proved, whereas Drain Current Transient Spectroscopy (DCTS) provides information about the location of traps in the structure. Experimental results establish the complementarity of these two techniques.

The pseudomorphic AlGaAs/InGaAs/GaAs MODFET, intended for future applications in cryoelectronics, has been investigated. In the temperature range of 10–350 K no collapse nor Kink effect have been detected. However, a threshold shift has been observed which is thought to be associated with electrically active defects in the heterostructure. The related deep levels are directly characterized by two electrical techniques: capacitance deep level transient spectroscopy and drain current transient spectroscopy. Experimental results establish the complementarity of both techniques.

Fast GaAs Metal–Semiconductor Field-Effect-Transistor (MESFET) on InP exhibiting promising performances comparable to those grown on GaAs subtrates have already been fabricated. The lattice mismatch of 4% between GaAs and InP did not preclude device fabrication, although the characterization of such materials has shown the existence of high dislocation density at the interface and a residual biaxial tensile strain due to the difference between the thermoelastic properties of the two materials. The above-mentioned growth difficulties can generate many defects, which are very detrimental for device application. In this context, we have investigated deep levels on Rapid Thermal Annealed (RTA) GaAs/InP MESFET by means of Drain-Current Deep-Level Transient Spectroscopy (CDLTS). In this study, we have revealed the absence of dislocation-generated-deep level, the formation of an apparent “hole-like” observed for the first time with an activation energy of 0.3 eV. On comparison with homo-epitaxial GaAs MESFET achieved under the same conditions, we note the absence of a deep level with an apparent activation energy of 0.4 eV.

Deep levels in AlGaN/GaN HEMTs on Si substrate are known to be responsible for trapping processes like: threshold voltage shift, leakage current, degradation in saturation current and hysteresis effect. The related deep levels are directly characterized by Conductance Deep Level Transient Spectroscopy (CDLTS) method. Hereby we have detected four carrier traps with activation energy of 0.83, 0.50, 0.20 and 0.07 eV and capture cross-section respectively of σ = 3.14 × 10 − 14 cm 2 , σ = 2.57 × 10 − 15 cm 2 , σ = 3.03 × 10 − 17 cm 2 and σ = 2.65 × 10 − 15 cm 2 . All these traps are located between the substrate and the two-dimensional electron gas (2DEG) channel.

In a forward-biased Schottky diode, the charge of the interface states can be electrically modulated. This results in the appearance of additional capacitance whose variations with frequency, bias and temperature can be used to determine the characteristic parameters of the states (energy position, density, capture cross sections). A simple model is described, taking into account any possible charge exchanges between the interface states and the three 'reservoirs' surrounding them (conduction and valence bands of the semiconductor and conduction band of the metal). Limit cases where one or two of these exchange paths are dominant are detailed and a few typical experimental examples are given.

A study of the capacitance of a forward biased Schottky diode as a function of bias, temperature, and frequency allows characterization of interface states at the metal‐semiconductor junction. This method, called Schottky Capacitance Spectroscopy is applied to interfaces obtained by evaporating Au, Ag, or Al onto n‐type cleaved GaAs 〈110〉 surfaces. We have explored the region of the semiconductor band gap about 1 eV below the conduction band minimum. There is evidence of three kinds of states. The energy levels of these states are quite reproducible while we have obtained a light dispersion of density of states and capture cross sections. Moreover, we have observed a correlation between the relative density of states C and the degradation of the I–V characteristic.

It is generally accepted that the conduction in Schottky diodes follows the thermionic model, corrected by an empirical non-ideality parameter, n , slightly higher than unity. But very often experimental curves of (log I ) V exhibit slope discontinuities which, at first sight, are not compatible with this model. We try here to characterize and to classify the various types of anomalies experimentally encountered in metal-III–V semiconductor contacts and to put forward plausible explanations.

Schottky capacitance spectroscopy is an electrical method allowing the characterization of interface states at a metal‐semiconductor junction. This method is based on the study of the capacitance of a forward biased Schottky diode as a function of bias, temperature, and frequency. The experimental procedure previously described presents the drawback of being very time consuming because of the need for low‐frequency measurements. We describe here a new improved method allowing rapid and straightforward spectroscopy with high‐energy resolution.

Al growth by MBE has been achieved onto {001} GaAs surfaces with different reconstructions and stoichiometries. No correlation is observed between the initial surface characteristics and the barrier height of the obtained Schottky diodes. A study of interface states distribution by Schottky Capacitance Spectroscopy shows three kinds of states in the upper half of the gap. These states are not markedly affected by surface stoichiometry variations.

Conductance DLTS measurements performed on 4H-SiC MESFETs shows "hole-like" traps peaks. These levels are associated with surface states. The conductance measurements are interpreted using a model previously developed for GaAs MESFETs which involves the presence of an interface conducting layer between the channel and the passivating layer (SiC/SiO/sub 2/ in our case).

Schottky capacitance spectroscopy is applied to interfaces between UHV cleaved gallium arsenide 〈110〉 surfaces and various metals (Au, Ag, Al). The study is done simultaneously on n-type and p-type semiconductor. Various interface states located in the band gap are evidenced. The type of the metal influences only their density but does not modify their energy position. Among detected states, two of them are located at energies around Ec − 0.7 eV and Ev + 0.5 eV. These positions seem to be in agreement with those of the defect states responsible, according to Spicer et al., for the Fermi-level pinning during the first stage of metal atom disposition.