1. 22 μW, 5.1 ps LSB, 5.5 ps RMS jitter Vernier time‐to‐digital converter in CMOS 65 nm for single photon avalanche diode array
- Author
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S. Carrier, R. Fontaine, N. Roy, F. Nolet, Jean-Francois Pratte, Serge A. Charlebois, and Jonathan Bouchard
- Subjects
Physics ,business.industry ,Dynamic range ,Vernier scale ,020208 electrical & electronic engineering ,Detector ,02 engineering and technology ,Avalanche photodiode ,law.invention ,Time-to-digital converter ,CMOS ,Single-photon avalanche diode ,law ,0202 electrical engineering, electronic engineering, information engineering ,Optoelectronics ,Electrical and Electronic Engineering ,business ,Jitter - Abstract
A Vernier ring-oscillator-based time-to-digital converter (TDC) with a new prelogic is presented. Experimental results show that the proposed architecture achieve a 5.5 ps RMS timing jitter with a 5.1 ps LSB within an area of 0.00151 mm 2 . Thanks to the new prelogic circuit, the power consumption of the circuit was optimised to 22 μ W at a rate of 1 Mevents/s for a dynamic range of 4 ns. The area, timing jitter and power consumption make the TDC suitable for an array of electronic readout in a position emission tomography single photon avalanche diode based detectors.
- Published
- 2020
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