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Your search keyword '"F. Paillardet"' showing total 6 results
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6 results on '"F. Paillardet"'

1. 40-nm RFSOI technology exhibiting 90fs RON × COFF and fT/fMAX of 250 GHz/350 GHz targeting sub-6 GHz and mmW 5G applications.

Author

S. Crémer, N. Pelloux, F. Gianesello, Y. Mourier, G. Haury, Tulio Chaves de Albuquerque, Frederic Monsieur, H. Audouin, C. A. Legrand, C. Diouf, J. Azevedo Goncalves, C. Belem Goncalves, C. Durand, N. Vulliet, L. Berthier, Emeline Souchier, P. Garcia, S. Jan, M. Hello, M. L. Rellier, Patrick Scheer, B. Duriez, Xavier Garros, T. Bordignon, F. Paillardet, and Pascal Chevalier 0002

Published
2023
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4. A 3.3 V 6 BITS 60 MHZ CMOS DUAL ADC

Author

P. Robert and F. Paillardet

Subjects
Offset cancellation, Engineering, Signal generator, Comparator, business.industry, Electrical engineering, Integrated circuit, Chip, Dual (category theory), law.invention, CMOS, law, Media Technology, Electronic engineering, Electrical and Electronic Engineering, business, Interpolation
Abstract

The paper describes a 6 bit dual A/D with a 60 MHz conversion rate in a 3.3 V 0.5 /spl mu/m CMOS process. It uses autozeroed comparators combined with interpolation and offset cancellation techniques. >

Published
2005
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5. A Novel OSD For Multistandard CVBS Applications

Author

J.P. Gavet, O. Queinnec, F. Paillardet, B. Schuster, and C. Delmas

Subjects
Video recording, Phase-locked loop, Engineering, CMOS, Band-pass filter, Application-specific integrated circuit, law, business.industry, Circuit design, Electronic engineering, Laser, business, law.invention
Abstract

Many OSD solutions are already available on the market for TV applications. Only a few are available for the VTR, SatellitdCable receivers and Laser Disc applications. This situation is mainly due to the fact that these applications are CVBS based (compared to WG/B based for TV) and that the circuit design is thus much more complex (especially with low cost CMOS A novel OSD has been designed to reach two goals: technology).

Published
2005
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6. A new characterization method for accurate capacitor matching measurements using pseudo-floating gate test structures in submicron CMOS and BiCMOS technologies

Author

G. Morin, E. Mazaleyrat, F. Paillardet, and O. Roux dit Buisson

Subjects
Engineering, Matching (statistics), business.industry, Electrical engineering, Hardware_PERFORMANCEANDRELIABILITY, BiCMOS, Characterization (materials science), law.invention, Capacitor, CMOS, Hardware_GENERAL, Test structure, law, Hardware_INTEGRATEDCIRCUITS, Electronic engineering, Hardware_ARITHMETICANDLOGICSTRUCTURES, Antenna (radio), business, Gate equivalent, Hardware_LOGICDESIGN
Abstract

In deep submicron CMOS and BiCMOS technologies, antenna effects affect the floating gate charge of conventional floating gate test structures, dedicated to capacitor matching measurement. In this paper, a new pseudo-floating gate test structure is designed. After test structure and modeling presentation, the testing method and results are given for several capacitor layouts (poly-poly and metal-metal).

Published
2002
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