Search

Two-dimensional ferroelectric materials are beneficial for power-efficient memory devices and transistor applications. Here, we predict out-of-plane ferroelectricity in a new family of buckled metal oxide (MO; M: Ge, Sn, Pb) monolayers with significant spontaneous polarization. Additionally, these monolayers have a narrow valence band, which is energetically separated from the rest of the low-lying valence bands. Such a unique band structure limits the long thermal tail of the hot carriers, mitigating subthreshold thermionic leakage and allowing field-effect transistors (FETs) to function beyond the bounds imposed on conventional FETs by thermodynamics. Our quantum transport simulations reveal that the FETs based on these MO monolayers exhibit a large ON/OFF ratio with an average subthreshold swing of less than 60 mV/decade at room temperature, even for short gate lengths. Our work motivates further exploration of the MO monolayers for developing advanced, high-performance memory and logic devices. [ABSTRACT FROM AUTHOR]

Low-frequency (LF) noise measurements are compared for Schottky-gate AlGaN/GaN heterostructure planar and fin field-effect transistors (FinFETs) as functions of gate voltage and measuring temperature. The noise of each device type is consistent with a carrier number fluctuation model. Similar effective defect-energy Eo distributions are derived for each of the two device architectures from measurements of excess drain-voltage noise-power spectral density vs temperature from 80 to 380 K. Defect- and/or impurity-related peaks are observed in the inferred energy distributions for Eo < 0.2 eV, Eo ≈ 0.45 eV, and Eo > 0.6 eV. Significant contributions to the LF noise are inferred for nitrogen vacancies and ON and FeGa impurity complexes. Ga dangling bonds at fin interfaces with gate metal are likely candidates for enhanced noise observed in FinFETs, relative to planar devices. Reducing the concentrations of these defects and impurity complexes should reduce the LF noise and enhance the performance, reliability, and radiation tolerance of GaN-based high electron mobility transistors. [ABSTRACT FROM AUTHOR]

N-type carbon nanotubes (CNTs)-based field-effect transistors (FETs) have huge potential applications in low-power consumption tunnel FETs. However, the low-work function metal electrodes can achieve n-type CNTs, but they are easily oxidized due to poor environmental stability. Therefore, based on first-principles calculations, we proposed halide perovskite nanowires Cs4MX5 (M = Pb, Sn; X = Cl, Br, I) inner filling to achieve n-type single-walled CNTs (SWCNTs). The results indicated that all the perovskite nanowires located at the center of the SWCNTs possess high stability. Moreover, the diameter of SWCNTs is a crucial factor affecting the inner filling of perovskite nanowires with an optimal diameter of about 1.4 nm. Furthermore, all the perovskite nanowires Cs4MX5 are excellent electron donors, and the largest charge transfer is up to 1.72 e/nm for Cs4SnI5. Their interaction mechanism reveals that the low work function and the large internal bandgap are two important factors for cubic-phase nanowires to realize the n-type CNTs. Our findings provide some candidate materials and a feasible way to achieve n-type CNTs for applying CNTs-based FETs. [ABSTRACT FROM AUTHOR]

We investigate the MX2 (M = {Hf, Zr}, X = {S, Se}) transition metal dichalcogenides patterned into armchair (AC) and zigzag (ZZ) nanoribbons (NRs) as potential channel materials in future logic field-effect devices. Ab initio quantum transport simulations are employed to assess the electronic, transport, and ballistic field-effect transistor (FET) properties of devices with such quasi-one-dimensional channels. We report a non-monotonic scaling behavior of MX2NR properties due to strong quantum confinement effects, which is reflected in a strong dependence of the ON-state current (ION) of MX2NR FETs on the nanoribbon configuration. The ∼2 nm-wide HfSe2 and ZrSe2 AC-PFETs have the highest ION of up to 2.6 mA/μm at 10 nA/μm OFF-state current. Surprisingly, MX2NR ZZ-NFETs exhibit a current increase of up to 70% when channel width is scaled down, with ION reaching 2.2 mA/μm in ∼2 nm-wide devices. The high ON-state performance is a direct consequence of high carrier injection velocity, which is explained by analyzing the band structure, transmission, and density of states. We demonstrate that nanostructured MX2 materials can be promising candidates for future logic transistors based on multi-nanowire architectures. [ABSTRACT FROM AUTHOR]

The deep-level drain current transient spectroscopy (Id-DLTS) measurements of Al -doped SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) strongly suggest that the reduction in the channel mobility at low temperatures is related to a shallow trap detectable at 70 K. Using the Shockley–Reed–Hall (SRH) theory, the level of this trap has been extracted to be around 0.15 eV below the conduction band minimum of SiC. Density functional theory (DFT) calculations of Al Si N C Al Si and Al Si O C Al Si defect complexes have found one configuration of the Al Si O C Al Si complex, which has a charge transition level within the SRH extracted trap level range. Therefore, we suggest that these Al Si O C Al Si defects are likely candidates for traps responsible for the channel mobility reduction. [ABSTRACT FROM AUTHOR]

Large Schottky barriers formed at the interfaces between graphene and 2D semiconductors often degrade device performance. Here, taking the Janus MoSO as a prototype and using the first-principles calculations together with the band unfolding technique, we demonstrate that the Ohmic contact (OC), which is absent in pristine graphene/MoXY (X/Y = S, Se, Te. X ≠ Y), is realized in the pristine graphene/MoSO (G/MoSO) heterostructure. G/OMoS shows the n -type OC (OC- n) that leads to the p -doping of the graphene layer with a hole density of 1.17 × 10 13 /cm 2 , while G/SMoO exhibits the p -type Schottky contact with a tunable Schottky barrier height. The realization of OC and the interface dependent contact type are mainly attributed to the large intrinsic dipole between asymmetric S and O layers, which dominate the different behaviors of charge transfer and the associated interface dipole in heterostructures. Inspired by the finding, considering the larger dipole moment in Janus MoSeO and MoTeO, we further confirm that both OC- n and OC- p exist in pristine G/MoSeO and G/MoTeO. Moreover, on comparison with MoSO, both G/OMoS and G/SMoO show enhanced optical absorptions (∼ 10 5 cm − 1 ) in most of the visible light range. Our results not only show the potential application of G/MoSO in nanoelectronic devices such as field-effect transistors but also indicate that dipole engineering would help us to predict or design desirable electric contacts of Janus-transition metal dichalcogenide-based metal/semiconductor systems in advance. [ABSTRACT FROM AUTHOR]

The successful synthesis and discovery of unique properties in two-dimensional Janus materials have positioned them as promising candidates for applications in sensors, field-effect transistors, and ultrasensitive detectors. In this study, we utilized first-principles calculations to predict a novel Janus CeIBr monolayer. Our calculations show that Janus CeIBr monolayer behaves as a bipolar magnetic semiconductor, demonstrating both mechanical and thermodynamic stability, along with a high Curie temperature of 242 K and in-plane magnetic anisotropy (102.92 meV). A notable intrinsic valley splitting of 66 meV is also evident in CeIBr, highlighting its distinctive valley contrast characteristic. Furthermore, the application of biaxial strain effectively transforms the magnetic ground state of CeIBr from a ferromagnetic state to an antiferromagnetic state and alters the direction of the easy magnetization axis from in-plane to out-of-plane. Our findings offer a theoretical foundation for the design of novel anomalous valley Hall effect-based electronic devices utilizing the Janus CeIBr monolayer. [ABSTRACT FROM AUTHOR]

Carbon nanotubes have shown great promise for high-performance, large-area, solution processable field-effect transistors due to their exceptional charge transport properties. In this study, we utilize the spin-coating method to form networks from selectively sorted semiconducting single-walled carbon nanotubes (s-SWNTs), aiming for scalable electronic device fabrication. The one-dimensional nature of s-SWNTs, however, introduces significant roughness and charge trap sites, hindering charge transport due to the van der Waals gap (∼0.32 nm) between nanotubes. Addressing this, we explored the effects of anion doping on the spin-coated s-SWNT random network, with a focus on the influence of the small size of halogen anions (0.13–0.22 nm) on these electronic properties. Raman and ultraviolet–visible–near-infrared optical spectroscopy results indicate that smaller anions significantly enhance doping effects through strong non-covalent anion–π interactions, improving charge transport and carrier injection efficiency in s-SWNTs, especially for n-type operation. This improvement is inversely proportional to the size of the halogen anions, with the smallest anion (fluorine) effectively transitioning the electrical characteristics of the s-SWNT network from ambipolar to n-type by reducing both junction and contact resistances through anion doping, based on anion–π interaction. [ABSTRACT FROM AUTHOR]

The two-dimensional (2D) Ruddlesden−Popper phase all-inorganic halide perovskite Cs2PbI2Cl2 has attracted tremendous attention because of its high carrier mobility, strong light-absorbing ability, and excellent environmental stability, possessing enormous potential for use as a high-performance optoelectronic device. Here, we present two transistor devices based on monolayer (ML) Cs2PbI2Cl2 and reveal their performance and current transport mechanisms through ab initio quantum transport calculations. The n-type 10 nm metal-oxide-semiconductor field-effect transistor shows a high on-state current Ion of 3160 μA/μm, and excellent performance regarding subthreshold swing, intrinsic delay time (τ), and power consumption, which completely match the International Roadmap for Device and Systems (2021 version) targets for high-performance devices and low-power devices in 2028. Moreover, phototransistors based on monolayer Cs2PbI2Cl2 also display a strong response to UV light, with a light-to-dark current ratio reaching a maximum of 104. Meanwhile, a high specific detectivity of 2.45 × 1011 Jones is obtained. The results of our study suggest that ML Cs2PbI2Cl2 is a promising candidate for high-performance transistors. [ABSTRACT FROM AUTHOR]

4H-SiC/ SiO 2 interface states play a major role in the performance and reliability of modern 4H-SiC metal–oxide–semiconductor field effect transistors (MOSFETs). To gain new insights into these interface states, we developed a cryogenic measurement technique that uses photon-assisted electron depopulation to probe device performance limiting 4H-SiC/ SiO 2 interface states. This technique enables the characterization of shallow as well as deep states at the 4H-SiC/ SiO 2 interface of fully processed devices using a cryogenic probe station. Our method is performed on n-channel 4H-SiC MOSFET test structures with deposited oxide and postoxidation anneal. We identify conditions under which the electrons remain trapped at 4H-SiC/ SiO 2 interface states and trigger the controlled photon-assisted electron depopulation within a range of photon energies. This allows us to prove the presence of near interface traps, which have previously been found in thermally grown 4H-SiC MOS structures. Our results are supported by device simulations. Additionally, we study the impact of irradiation intensity and light exposure time on the photon-induced processes. [ABSTRACT FROM AUTHOR]

We propose a main mechanism of large valley splitting experimentally observed at the interface of buried oxide (BOX)/silicon-on-insulator (SOI) structures. Silicon metal-oxide-semiconductor field effect transistors fabricated on a SIMOX (001) substrate, which is a kind of the SOI substrate, that is annealed at high temperatures for a long time are known to exhibit large valley splitting, but the origin of this splitting has long been unknown. Extended zone effective-mass approximation predicts that strain significantly affects valley splitting. In this study, we analyzed valley splitting based on this theory and found that the shear strain along [110] of approximately 5% near the BOX interface is a promising source for large valley splitting. [ABSTRACT FROM AUTHOR]

The ultra-wide bandgap of gallium oxide provides a rich plethora of electrically active defects. Understanding and controlling such defects is of crucial importance in mature device processing. Deep-level transient spectroscopy is one of the most sensitive techniques for measuring electrically active defects in semiconductors and, hence, a key technique for progress toward gallium oxide-based components, including Schottky barrier diodes and field-effect transistors. However, deep-level transient spectroscopy does not provide chemical or configurational information about the defect signature and must, therefore, be combined with other experimental techniques or theoretical modeling to gain a deeper understanding of the defect physics. Here, we discuss the current status regarding the identification of electrically active defects in beta-phase gallium oxide, as observed by deep-level transient spectroscopy and supported by first-principles defect calculations based on the density functional theory. We also discuss the coordinated use of the experiment and theory as a powerful approach for studying electrically active defects and highlight some of the interesting but challenging issues related to the characterization and control of defects in this fascinating material. [ABSTRACT FROM AUTHOR]

In this paper, the p-GaN gate AlGaN/GaN high electron mobility transistors (HEMTs) with varying combinations of gate metal work function and gate geometry are fabricated and investigate the influence of gate leakage current (IGS) on the threshold voltage (VTH) and subthreshold swing (SS). The unique dependence of VTH and SS on gate geometry for different metals is observed, which is different from traditional field-effect transistors. A novel hybrid physics model, consisting of the traditional capacitance divider model and hole injection model, is proposed to explain this phenomenon, and the results exhibit an excellent agreement with the experimental data. The holes traverse the gate/p-GaN Schottky barrier by thermal emission or tunneling and inject into the p-GaN layer, generating the IGS. Expanding upon the traditional capacitance divider model, a portion of the injected holes accumulate at the p-GaN/AlGaN interface and induce the corresponding electrons at the AlGaN/GaN heterojunction, which promotes channel conduction. Hence, the transfer curves display the correlation between IGS and VTH as well as SS. The results show that high IGS can alleviate the instability of VTH caused by the lithographic overlay error, and simultaneously optimize SS. This work offers a novel perspective for examining the turn-on mechanism of p-GaN HEMTs, thereby contributing to device design. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a hydrogen-terminated diamond (H-diamond) field-effect transistor (FET) with Al2O3/CeB6 gate materials. The CeB6 and Al2O3 films have been deposited by electron beam evaporation technique, sequentially. For the 4/8/12/15 μm gate length (LG) devices, the whole devices demonstrate distinct p-type normally off characteristics, and all the threshold voltage are negative; all the absolute values of leakage current density are 10−4 A/cm2 at a VGS of −11 V, exhibiting a relatively low leakage current density compared with CeB6 FETs, and this further demonstrates the feasibility of the introduction of Al2O3 to reduce the leakage current density; the maximum drain–source current density is −114.6, −96.0, −80.9, and −73.7 mA/mm, which may be benefited from the well-protected channel. For the 12 μm LG devices, the saturation carrier mobility is 593.6 cm2/V s, demonstrating a good channel transport characteristic. This work may provide a promising strategy for the application of normally off H-diamond FETs significantly. [ABSTRACT FROM AUTHOR]

Molybdenum disulfide (MoS2), a semiconducting two-dimensional layered transition metal dichalcogenide (2D TMDC), with attractive properties enables the opening of a new electronics era beyond Si. However, the notoriously high contact resistance (RC) regardless of the electrode metal has been a major challenge in the practical applications of MoS2-based electronics. Moreover, it is difficult to lower RC because the conventional doping technique is unsuitable for MoS2 due to its ultrathin nature. Therefore, the metal–insulator–semiconductor (MIS) architecture has been proposed as a method to fabricate a reliable and stable contact with low RC. Herein, we introduce a strategy to fabricate MIS contact based on atomic layer deposition (ALD) to dramatically reduce the RC of single-layer MoS2 field effect transistors (FETs). We utilize ALD Al2O3 as an interlayer for the MIS contact of bottom-gated MoS2 FETs. Based on the Langmuir isotherm, the uniformity of ALD Al2O3 films on MoS2 can be increased by modulating the precursor injection pressures even at low temperatures of 150 °C. We discovered, for the first time, that film uniformity critically affects RC without altering the film thickness. Additionally, we can add functionality to the uniform interlayer by adopting isopropyl alcohol (IPA) as an oxidant. Tunneling resistance across the MIS contact is lowered by n-type doping of MoS2 induced by IPA as the oxidant in the ALD process. Through a highly uniform interlayer combined with strong doping, the contact resistance is improved by more than two orders of magnitude compared to that of other MoS2 FETs fabricated in this study. [ABSTRACT FROM AUTHOR]

The rising temperature due to a self-heating or thermal environment not only degrades the subthreshold performance but also intensifies thermal stress, posing a severe challenge to device performance and reliability design. The thermal stress effects on the ON-state performance of the p-type fin field-effect transistor were previously studied. However, as far as we know, how thermal stress affects its subthreshold conduction remains unclear, which is studied in this manuscript. The impact of thermal stress due to the self-heating of adjacent devices on subthreshold conduction is investigated by solving the quantum transport, thermal conduction, and force balance equations for ballistic transport and dissipative transport with phonon scattering. Then, the thermal stress effects at different ambient temperatures are further discussed and analyzed. The simulation results show that the OFF-state leakage current can be reduced by thermal stress, even up to 9.28% for the (110)/[001] device operating at an ambient temperature of 550 K, and its reduction is the comprehensive result of the thermal stress effects on the band structure, potential profile, carrier distribution, and source-to-drain tunneling. In addition, the thermal stress has no significant effects on subthreshold swing although it can change the magnitude of the subthreshold current. Moreover, the effect of thermal stress on subthreshold conduction is highly dependent on the thermal environment of the device and the crystal orientation of the channel semiconductor material. [ABSTRACT FROM AUTHOR]

The performance of SiC-based metal-oxide-semiconductor field-effect transistors (MOSFETs) degrades seriously after a period of continuous operation. To directly understand this issue, we conduct real-time time-dependent density functional theory (TDDFT) simulations on a series of nitrogen passivated SiC– SiO 2 interfaces to monitor the interaction between carriers and interface atoms. We find that the nitrogen passivation always leaves behind two local states near the VBM, which gives a chance to the strong interaction between channel carriers and C–N bonds, and finally results in the generation of C dangling bond defects. These processes are vividly presented and confirmed by the TDDFT simulation. Additionally, the results show that the new defects are more easily formed by the passivated C cluster than the passivated Si vacancy. These studies provide physical insights into the degradation mechanisms of working SiC MOSFETs, while simultaneously demonstrating the advantage of TDDFT as a crucial tool for investigating defect generation dynamics in semiconductor devices. [ABSTRACT FROM AUTHOR]

Gallenene is a novel metallic 2D material that can provide a semiconducting counterpart if patterned into quasi-one-dimensional (quasi-1D) nanostructures, i.e., gallenene nanoribbons (GaNRs). We investigate semiconducting GaNRs as a potential channel material for future ultrascaled field-effect transistors (FETs) by employing quantum transport simulations based on Green's functions and tight-binding Hamiltonians with the orbital resolution calibrated on ab initio calculations. The impact of GaNR width downscaling from ∼6 nm down to ∼0.2 nm on the electronic, transport, and ballistic device properties is investigated for the FET channel length of 15 nm. We report current enhancement and injection velocity overshoot effects for sub-1.2 nm-wide nFETs and pFETs, with a maximum current increase of 53% in the 1.2 nm-wide GaNR pFET in comparison to the widest device. In addition, promising current-driving capabilities of n- and p-channel GaNR FETs are observed with top ballistic currents of more than 2.2 mA/μm and injection velocities of up to 2.4 × 107 cm/s. The reported data are explained by analyzing the evolution of band structure and related parameters such as injection velocity, quantum capacitance, effective transport mass etc., with increasing quantum confinement effects in ultranarrow GaNRs. Generally, we find that quasi-1D gallenene is a promising channel material for future nanoscale FETs, especially for transistor architectures based on stacked nanosheets. [ABSTRACT FROM AUTHOR]

Negative differential resistance (NDR) is observed in various emerging electronic devices. As compared to the conventional silicon-based field effect transistor (FET), the NDR is widely investigated in two-dimensional (2D) transition metal dichalcogenide (TMD) FETs. In this work, we study the NDR effect for the TMD-based metal-edge-contact MoS 2 double-gate FET with 10 nm channel length. The multiscale atomistic simulation is demonstrated for the lateral heterostructure of a metal–semiconductor–metal FET by density functional theory, maximally localized Wannier function tight-binding Hamiltonian, and non-equilibrium Green's function methods. The quantum transport model in the given lateral heterostructure resulted in NDR in a double-gate FET. Here, we focus on the NDR by the systematic study of the transmission spectrum of the metal-edge-contact MoS 2 channel FET and finally compare it with zero NDR ideal highly doped FET. The peak-to-valley ratio in the NDR response can be modulated with the change in the gate-to-source voltage and can be used to explore various future electronic applications. [ABSTRACT FROM AUTHOR]

With the proportional reduction of metal–oxide–semiconductor field effect transistor (MOSFET) devices, the short channel effect, the parasitic effect, and the field strength effect are significantly enhanced, the proportion of parasitic resistance increases, and the non-intrinsic noise also increases, which seriously affects the working efficiency of the device. However, existing research mainly focuses on the intrinsic noise of MOSFET, and there is little research on the non-intrinsic noise; furthermore, the models describing the relationship between non-intrinsic noise, device structure, and bias have not yet been addressed. Therefore, in this paper, 90, 65, 32, 10, and 5 nm MOSFETs are studied. The rate of the intrinsic ballistic parameter is introduced to set up the source–drain current model and the non-intrinsic noise model. The source–drain current model is consistent with the theoretical model, numerical simulation, and experimental results in the literature. Finally, the relationship between the non-intrinsic noise and the bias and the device parameters are analyzed, and the conclusion is helpful to improve the working efficiency, lifetime, and response speed of nanoscale MOSFET devices. [ABSTRACT FROM AUTHOR]

Gallium oxide (G a 2 O 3 ) is a promising ultra-wide bandgap material offering a large bandgap (> --> 4.7 eV) and high critical electric fields. The increasing demand for electronic devices for high-power applications in electric automobiles, high-performance computing, green energy technologies, etc., requires higher voltages and currents with enhanced efficiency. Vertical transistors, such as fin-shaped field-effect transistors (FinFETs) have emerged to meet the growing need with improved current handling capabilities, reduced resistance, and enhanced thermal performance. However, to fully exploit the Ga 2 O 3 power transistors, precise and reliable physics-driven models are crucial. Therefore, a comprehensive surface potential model has been developed in this work for a vertical Ga 2 O 3 FinFET. The electric potential across the channel is explained by analyzing the two-dimensional (2D) Poisson equation employing parabolic approximation. Such a surface potential model is instrumental in determining the performance of the Ga 2 O 3 FinFET as it affects the threshold voltage, the drain current, and fringing capacitance. Exploiting the surface potentials, a fringing capacitance model is derived which is crucial in analyzing the speed of the device in compact integrated circuits. In addition, statistical analysis of the Ga 2 O 3 FinFET using the Monte Carlo simulation technique is performed to determine the leakage current fluctuation due to doping variations. The validation of the analytical model with experimental results confirms the effectiveness and prospects of the developed models in the rapid development and characterization of next-generation high-performance vertical Ga 2 O 3 power transistors. [ABSTRACT FROM AUTHOR]

The recent progress in quantum computing and space exploration led to a surge in interest in cryogenic electronics. Superconducting devices such as Josephson junction, Josephson field effect transistor, cryotron, and superconducting quantum interference device (SQUID) are traditionally used to build cryogenic logic gates. However, due to the superconducting nature, gate-voltage-based control of these devices is extremely difficult. Even more challenging is to cascade the logic gates because most of these devices require current bias for their operation. Therefore, these devices are not as convenient as the semiconducting transistors to design logic gates. Here, to overcome these challenges, we propose a ferroelectric SQUID (FeSQUID) based voltage-controlled logic gates. FeSQUID exhibits two different critical current levels for two different voltage-switchable polarization states of the ferroelectric. We utilize the polarization-dependent (hence, voltage-controllable) superconducting to resistive switching of FeSQUID to design Boolean logic gates such as Copy, NOT, AND, and OR gates. The operations of these gates are verified using a Verilog-A-based compact model of FeSQUID. Finally, to demonstrate the fanning out capability of FeSQUID-based logic family, we simulate a two-input XOR gate using FeSQUID-based NOT, AND, and OR gates. Together with the ongoing progress on FeSQUID-based non-volatile memory, our designed FeSQUID-based logic family will enable all FeSQUID-based cryogenic computer, ensuring minimum mismatch between logic and memory blocks in terms of speed, power consumption, and fabrication process. [ABSTRACT FROM AUTHOR]

For over half a century, traditional silicon-based integrated circuits (ICs) have been the basis of computational electronics and are widely used in computers, cell phones, and other fields. With the rapid development of human society, silicon-based semiconductor technology is approaching its physical and engineering limits. Our increasing diversity of non-traditional computing needs, such as ultra-small, ultra-fast, ultra-low-power wearables, and space radiation protection, is driving the search for new electronic materials. Semiconducting single-walled carbon nanotubes (s-SWCNTs) have many excellent electrical properties, such as high carrier mobility and high ballistic transport, making them strong candidates for new semiconductor materials in the post-Moore era. Carbon-based electronic technology has been developed for over 20 years, and the fundamental issues such as the material purification of s-SWCNTs, preparation prospects of s-SWCNT-based field-effect transistors (CNT FETs), and device physics based on CNT FETs have been basically solved. However, the chiral diversity of s-SWCNTs may lead to problems such as fluctuations in the electrical performance of CNT FETs, limiting the application of s-SWCNTs in high-end ICs. Monochiral s-SWCNTs not only have excellent electrical properties but also have a controllable structure and uniformity, which are crucial for the high-end IC of CNTs. However, some problems exist in the purity and yield of monochiral s-SWCNT preparation and the optimization of monochiral CNT FETs. Therefore, the chiral sorting of CNTs is reviewed in this paper, and the progress of polymer reprocessing in chiral separation is highlighted. Then, the research progress of monochiral CNT FETs is introduced, and possible development directions are summarized and analyzed. Finally, the application prospects of chiral-enriched s-SWCNTs include challenges and future opportunities. [ABSTRACT FROM AUTHOR]

The relocation of peripheral transistors from the front-end-of-line (FEOL) to the back-end-of-line (BEOL) in fabrication processes is of significant interest, as it allows for the introduction of novel functionality in the BEOL while providing additional die area in the FEOL. Oxide semiconductor-based transistors serve as attractive candidates for BEOL. Within these categories, In2O3 material is particularly notable; nonetheless, the excessive intrinsic carrier concentration poses a limitation on its broader applicability. Herein, the deposition of Hf-doped In2O3 (IHO) films via atomic layer deposition for the first time demonstrates an effective method for tuning the intrinsic carrier concentration, where the doping concentration plays a critical role in determine the properties of IHO films and all-oxide structure transistors with Au-free process. The all-oxide transistors with In2O3: HfO2 ratio of 10:1 exhibited optimal electrical properties, including high on-current with 249 µA, field-effect mobility of 13.4 cm2 V−1 s−1, and on/off ratio exceeding 106, and also achieved excellent stability under long time positive bias stress and negative bias stress. These findings suggest that this study not only introduces a straightforward and efficient approach to improve the properties of In2O3 material and transistors, but as well paves the way for development of all-oxide transistors and their integration into BEOL technology. [ABSTRACT FROM AUTHOR]

Theoretical models have predicted that pH-responsive surface groups can reduce the sensitivity of field-effect transistor biosensors. However, attempts to prove this experimentally have shown conflicting results. In this work, a graphene field effect transistor (gFET) biosensor is used, which, without modification, is pH insensitive. The surface of the graphene is then functionalized using 1-hydroxypyrene to modulate the pH sensitivity of the gFET. A pH sensitivity ranging from 3.9 to 36.8 mV/pH was demonstrated. The biosensitivity of the gFETs was tested using streptavidin–biotin as a model system. The experimental results showed no correlation between biosensitivity and pH sensitivity. An electrochemical membrane model was used to determine the expected relationship between biosensitivity and pH sensitivity. The model results show that biosensitivity does not decrease until a certain threshold pH sensitivity is reached. This threshold is dependent on factors such as the acid dissociation constants of the surface hydroxyl groups and ion concentration. Furthermore, the differences between the simulation and experiment suggest that the effect of screening is greatly reduced when the analyte binds within a membrane. [ABSTRACT FROM AUTHOR]

In this study, the ungated AlGaN/GaN devices with special mesa structures were designed. The hypothesis of effective width expansion was tested experimentally by using ungated samples with different sizes, and an empirical expression for calculating the conduction channel effective width was given according to the experimental results. Finally, split-gate AlGaN/GaN heterostructure field-effect transistors (HFETs) with different gate lengths were prepared, and the channel electron mobility of split-gate samples was calculated by using the empirical expression and polarization Coulomb field (PCF) scattering theoretical model. The results showed that, for split-gate AlGaN/GaN HFETs, with the increase in the gate length, the total amount of additional polarization charges underneath the gate increases, resulting in the enhancement of the PCF scattering intensity. [ABSTRACT FROM AUTHOR]

This paper investigates near-interfacial charge trapping effects in graphene field-effect transistors with high-K gate dielectrics. Experimental and model-based analysis elucidates the impact of trapped charge on the transport properties of graphene. Landauer formalism is applied to correlate trapping-enhanced charged impurity scattering to degradation in conductivity and mobility. The analysis shows a significant reduction in conductivity and mobility with a transition toward the dominance of charge impurity scattering as evidenced by their dependence on the sheet carrier density. Moreover, we quantify the impact of trapped charge buildup on the carrier backscattering mean free path associated with charged impurities. This work provides new insights into the impact of charge trapping toward the development of logic, memory, and neuromorphic devices based on graphene and other low-dimensional materials and ultrascaled high-K dielectrics. [ABSTRACT FROM AUTHOR]

Graphene-based field-effect transistors (FETs) are suitable for pH sensors due to their outstanding surface chemical properties and its biocompatibility. To improve the devices' stability and pH sensitivity, different sets of dielectric passivation layers composed of monolayer hexagonal boron nitride with and without aluminum oxide layers were evaluated. Non-linearities of the pH response were observed. Heterostructure FETs were derived from subtractive manufacturing of commercially transferred two-dimensional materials on four-inch SiO2/Si wafers via stainless steel and polypropylene masking. Phosphate solutions (10 mM) of varying pH were incubated on bare devices, whereby liquid-gating elucidated linear changes in the Dirac voltage of hBN/graphene (−40 mV/pH) that was smaller than a device consisting only of monolayer graphene (−47 mV/pH). Graphene-based FETs were passivated with aluminum oxide nanofilms via electron beam or atomic layer deposition and were observed to have distinct Raman spectral properties and atomic force microscopy topologies corroborating the hypothesis that morphological differences of the deposited aluminum oxide influence the pH-dependent electrical properties. Atomic layer deposition of aluminum oxide on the 2D sensing areas resulted in non-linear shifting of the Dirac voltage with respect to pH that evolved as a function of deposition thickness and was distinct between graphene with and without hexagonal boron nitride as a capping monolayer. The non-linear response of varying thickness of AlxOy on graphene-based FETs was progressively reduced upon basic wet etching of the AlxOy. Overall, passivated graphene-based transistors exhibit deposition-dependent pH responses. [ABSTRACT FROM AUTHOR]

This study focuses on the electrical and optical properties of monolayer MoTe2 (1L‐MoTe2) flakes fabricated via gold‐mediated exfoliation, and it is demonstrated that this technique applies to the development of 1L‐MoTe2 channel field‐effect transistors (FETs). The average area of the gold‐exfoliated flakes is larger than that of conventional tape exfoliation. While the samples without an hBN cap layer are easily oxidized by atmospheric exposure for 1 day, increasing the number of nonradiative recombination centers, the surface oxidation of 1L‐MoTe2 can be suppressed by the deposition of the hBN cap layer. The transfer characteristics of the 1L‐MoTe2 channel FETs show clear ambipolar behavior and excellent switching properties, with an on/off ratio of 105. It is shown that graphite/1L‐MoTe2 junctions form a Schottky barrier with an energy of 280 meV, consistent with the theoretical value. By lowering the vacuum level, the gate voltage at the conductivity minimum point shifts to a negative value and the subthreshold swing decreases, implying a reduction in the interfacial trapped charge density due to the physisorption of O2/H2O molecules. These results demonstrate that the electrical properties of gold‐exfoliated 1L‐MoTe2 strongly depend on the environmental conditions. [ABSTRACT FROM AUTHOR]

Scandium‐doped aluminium nitride (ScxAl1‐xN)has made extensive progress in its applicationfor non‐volatile ferroelectric field effect transistors (FeFETs). However, ScAlN FeFET studies have mainly focused on memory devices based on n‐ and p‐type channel. Photodetectors based on ScAlN ferroelectric gatehave rarely been reported. Here, a FeFET device consisting of a metallic channel material, SnSe, and a ferroelectric gate material, Sc0.25Al0.75N is presented. Due to the different energy levels of Sc0.25Al0.75N and SnSe, a potential barrier is formed at the interface between them, which regulates the dark current and photoresponsivity of the heterostructure; meanwhile, the interfacial potential barrier is changed under three polarization states of Sc0.25Al0.75N. As a result, dark current of the device with Sc0.25Al0.75N gate is reduced by 104, on/off ratio is increased by 40 times, and the photoresponsivity is enhanced to 1 × 104 A W−1 compared with that of SiO2 gate; Moreover, on/off ratio of the devicesunder the positively polarized state is increased by nearly 103 underillumination; under the negatively polarized state, photoresponsivity reaches 5.4 × 105 and 3.1 × 104 A W−1 under illumination. This work demonstrates the feasibility of Sc0.25Al0.75N applied in FeFET photodetectors and opens up the possibility of developing ScAlN‐based optoelectronic devices. [ABSTRACT FROM AUTHOR]

This study discusses the feasibility of Ferroelectric Capacitors (FeCaps) and Ferroelectric Field-Effect Transistors (FeFETs) as In-Memory Computing (IMC) elements to accelerate machine learning (ML) workloads. We conducted an exploration of device fabrication and proposed system-algorithm co-design to boost performance. A novel FeCap device, incorporating an interfacial layer (IL) and Hf 0.5 Zr 0.5 O 2 (HZO), ensures a reduction in operating voltage and enhances HZO scaling while being compatible with CMOS circuits. The IL also enriches ferroelectricity and retention properties. When integrated into crossbar arrays, FeCaps and FeFETs demonstrate their effectiveness as IMC components, eliminating sneak paths and enabling selector-less operation, leading to notable improvements in energy efficiency and area utilization. However, it is worth noting that limited capacitance ratios in FeCaps introduced errors in multiply-and-accumulate (MAC) computations. The proposed co-design approach helps in mitigating these errors and achieves high accuracy in classifying the CIFAR-10 dataset, elevating it from a baseline of 10% to 81.7%. FeFETs in crossbars, with a higher on-off ratio, outperform FeCaps, and our proposed charge-based sensing scheme achieved at least an order of magnitude reduction in power consumption, compared to prevalent current-based methods. [ABSTRACT FROM AUTHOR]

In this work, the mechanistic insights behind low-frequency noise (LFN) of the advanced ultrathin body and buried oxide fully depleted silicon-on-insulator based metal–oxide–semiconductor field effect transistor (MOSFET) are unveiled. The gate voltage-induced noise power spectral density (SVG) is inversely proportional to frequency f (i.e., SVG ∝ 1 / f γ , γ ∼ 1 is the frequency exponent) for nMOSFET and pMOSFET. Detailed numerical simulations are performed and well calibrated to reported SVG vs f characteristics. Simulation results are consistent with the reported experimental observations. We demonstrate that LFN is caused by the charge carrier number fluctuation mechanism, which is originated by trapping and de-trapping of channel charge carriers via. bulk traps (from oxygen vacancies) in the hafnium dioxide (HfO2) layer, but not through traps at the silicon dioxide (SiO2)/channel interface. This work therefore explains the similar magnitude of SVG in both nMOSFET and pMOSFET observed experimentally and further suggests that oxygen vacancies inside gate oxides are critical to suppress the low-frequency noise in emerging high-k based MOSFETs. [ABSTRACT FROM AUTHOR]

In this Letter, a high-quality and high-resistivity nitrogen (N)-doped Ga2O3 current blocking layer (CBL) is grown utilizing metal-organic chemical vapor deposition homoepitaxial technology. By using nitrous oxide (N2O) as oxygen source for Ga2O3 growth and N source for doping and controlling the growth temperature, the grown CBL can effectively achieve high (∼1019 cm−3) or low (∼1017 cm−3) N doping concentrations, as well as high crystal quality. Furthermore, the electrical properties of the developed CBL are verified at the device level, which shows that the device using the CBL can withstand bidirectional voltages exceeding 3.5 kV with very low leakage (≤1 × 10−4 A/cm2). This work can pave the way for the realization of high-voltage and low-leakage Ga2O3 vertical devices, especially metal-oxide-semiconductor field effect transistors. [ABSTRACT FROM AUTHOR]

Nanoparticles of metal‐organic frameworks (nanoMOFs) possess the unusual combination of both internal and external surfaces. While internal surfaces have been the focus of fundamental and applications‐based MOF studies, the chemistry of the external surfaces remains scarcely understood. Herein we report that specific ion interactions with nanoparticles of Cu(1,2,3‐triazolate)2 (Cu(TA)2) resemble the Hofmeister behavior of proteins and the supramolecular chemistry of synthetic macromolecules. Inspired by these anion‐selective interactions, we tested the performance of Cu(TA)2 nanoparticles as chemical field effect transistor (ChemFET) anion sensors. Rather than size‐based selectivity, the detection limits of the devices exhibit a Hofmeister trend, with the greatest sensitivity towards anions perchlorate, iodide, and nitrate. These results highlight the importance of the pore‐based supramolecular interactions, rather than localized donor‐acceptor pairs, in designing MOF‐based technologies. [ABSTRACT FROM AUTHOR]

Highly sensitive biosensors which operate based on the utilization of random telegraph signal (RTS) noise spectroscopy might allow for the detection of diseases at the earliest stage. In this work, we provide an overview of our findings concerning RTS behavior in liquid-gated (LG) field-effect transistors (FETs). We propose different kinds of LG FET structures supported by modeling data for the extraction of characteristic RTS parameters for different carrier concentrations and operating voltages in the devices. We demonstrate the innovative aspects and opportunities of noise and fluctuations for biosensing applications. Moreover, we show that light excitation can be used to tune RTS parameters and increase the sensitivity of biosensors by at least 1.5 times. We also discuss challenges related to the utilization of RTS in different research fields, including biosensors and quantum information technology as well as ways of finding solutions to the problems. [ABSTRACT FROM AUTHOR]

Van der Waals (vdW) dielectrics are promising for enhancing the performance of nanoscale field-effect transistors (FETs) based on two-dimensional (2D) semiconductors due to their clean interfaces. Ideal vdW dielectrics for 2D FETs require high dielectric constants and proper band alignment with 2D semiconductors. However, high-quality dielectrics remain scarce. Here, we employed a topology-scale algorithm to screen vdW materials consisting of zero-dimensional (0D), one-dimensional (1D), and 2D motifs from Materials Project database. High-throughput first-principles calculations yielded bandgaps and dielectric properties of 189 0D, 81 1D and 252 2D vdW materials. Among which, 9 highly promising dielectric candidates are suitable for MoS2-based FETs. Element prevalence analysis indicates that materials containing strongly electronegative anions and heavy cations are more likely to be promising dielectrics. Moreover, we developed a high-accuracy two-step machine learning (ML) classifier for screening dielectrics. Implementing active learning framework, we successfully identified 49 additional promising vdW dielectrics. This work provides a rich candidate list of vdW dielectrics along with a high-accuracy ML screening model, facilitating future development of 2D FETs. New van der Waals (vdW) dielectrics with high dielectric constants are required to enhance the performance of 2D electronic devices. Here, the authors report high-throughput first-principles calculations and a machine learning classifier to identify >50 promising vdW dielectrics suitable for 2D field-effect transistors. [ABSTRACT FROM AUTHOR]

Focusing on Rhenium disulfide (ReS2), a group VII transition metal di-chalcogenides (TMDC), being a promising contender system for future nanoelectronics and optoelectronics, here, we present an innovative pathway to experimentally achieve an almost barrier-free contact for the ReS2 field effect transistors (FETs) by using few layered graphene as contact electrodes, further supported by comparative first-principles analysis. Such barrier-free contacts enable the observation of metal-to-insulator transition with enhanced room temperature carrier mobility up to 25 cm2/Vs, linear Ids-Vds characteristic down to 80 K, along with the reduction of 1/f noise by more than two orders of magnitude. We further demonstrate a highly responsive gate- tunable phototransistor (R > 106 A/W) at an illumination wavelength of 633 nm. This work demonstrates a straightforward strategy to unlock the full potential of ReS2 for CMOS compatible future electronic and optoelectronic devices. [ABSTRACT FROM AUTHOR]

In this paper for the first time, we have studied various structures of nanosheet field-effect transistors (NSFET) and the effect of various devices and process parameters such as nanosheet width, length, interspacing, S/D doping, channel doping, random dopant fluctuations studied on these device structures. Comparative analysis has been done between JL-NSFET, GS-JL-NSFET, JL-SiGeNSFET and JL-GS-SiGeNSFET in terms of analog parameters. Nanosheet-based FETs are likely to be the successor of FinFET beyond the 5-nm node. NSFETs have better control over gate, variable sheet width and more current per device footprint which gives them the advantage of circuit design versatility. NSFET offers better gate control, better current and switching per device footprint. NSFETs are preferred over NWFETs due to better electrostatics, greater channel widths, decreased SCEs and increased device reliability. Above 5 nm technology nodes, stacked nanosheet (NS) GAAFETs are expected to replace FinFETs as they have improved gate control, variable sheet width and substantial current per device footprint, which allows for flexible circuit design. The GAA nanosheet (NS) FETs outperform FinFETs and NWFETs while requiring just straightforward fabrication techniques. NSFETs increase the effective width of the channel while maintaining sufficient current drivability in the specified footprint to provide enhanced electrostatic integrity, better per chip density and enhanced power performances.Comparative analysis in terms of various analog parameters like Ion, Ioff, Ion/Ioff ratio, sub-threshold slope and the effect of various device parameters were carried out for JL-NSFET, JL-GS-NSFET, JL-SiGeNSFET and JL-GS-SiGeNSFET. [ABSTRACT FROM AUTHOR]

The metal‐organic vapor phase epitaxy (MOVPE) method faces several challenges when used for the growth of N‐polar GaN on foreign substrates, including the presence of a rough surface morphology characterized by step bunching or hexagonal hillocks. In this study, it is aimed to address these issues by establishing optimal growth conditions for the MOVPE method, enabling the growth of N‐polar GaN/Al0.9Ga0.1N/AlN heterostructures with a smooth surface morphology on a vicinal sapphire substrate. The formation of 2D electron gas (2DEG) in N‐polar GaN/AlGaN/AlN prepared using MOVPE is discussed. Additionally, in the study, the impact of growth conditions, such as temperature and V/III ratio, on the electrical properties of N‐polar GaN is investigated. In the results, it is revealed that growth at lower temperatures and a V/III ratio of 30 000 effectively suppresses 3D growth. Moreover, an increase in the V/III ratio correlates with a decrease in residual impurity concentrations (C and H); hence, electron mobility improves. Moreover, the N‐polar GaN/AlGaN/AlN field‐effect transistor, grown under optimized conditions, exhibits a higher maximum drain–source current (IDmax). In these results, possibilities are broadened for the high performance of N‐polar GaN channel high‐electron‐mobility transistors through MOVPE. [ABSTRACT FROM AUTHOR]

The failure process caused by overvoltage stress in cascode GaN–field effect transistors (FETs) is discussed through single unclamped inductive switching (UIS) waveforms, burst UIS waveforms, and capacitance–voltage characteristic shifts. One of the critical disadvantages of GaN–high electron mobility transistors (HEMTs) is their lack of UIS withstand capability, primarily because there is no mechanism for removing holes generated by avalanche breakdown. The device failure is observed at the drain voltage peak in the single UIS, and sudden and random breaks are observed in the burst UIS even with the same overvoltage stress. Both hole and electron traps after the burst UIS are observed, and the failure position is at the chip edge. From these results, it is verified that cascode GaN–FETs are broken due to time‐dependent dielectric breakdown of passivation films. [ABSTRACT FROM AUTHOR]

In this paper, two substrate optimization approaches for triple stacked nanosheet field-effect transistors (SNSHFETs), namely the optimization of buried oxide and the selective deposition of punch-through-stopper (PTS) substrate, have been examined, and simulations have been carried out using technology computer-aided software. A comprehensive study of the leakage current and key electrical characteristics (I ON, V T, subthreshold swing, drain-induced barrier lowering) has also been performed based on variations in temperature from 298 K to 450 K, sheet width, fin pitch, substrate width, and source/drain doping, as well as different substrates. When the ambient temperature of the SNSHFET is varied from 298 K to 450 K, the gate-induced drain leakage (GIDL) current increases and degrades the V T and I ON/ I OFF ratio. The GIDL current also increases with increased doping of the source and drain. The impact of ultra-thin body substrate in the SNSHFET is also studied for the reduction in GIDL current and optimization in the performance. It is observed that a reduction in the substrate width and the nanosheet width decreases the GIDL current, while variation in the inter-fin pitch has no significant impact on the GIDL current and other electrical characteristics. The band-to-band tunneling rate and electric field profiles are observed in the channel–drain and gate–substrate overlap regions to understand the physical insights of leakage current in the SNSHFET. This work also clarifies the dependency of the GIDL current on the gate and drain voltage supply, respectively. In addition, how the GIDL current responds to the variation in the source–drain doping and with different PTS doping has been explained. A 3 nm SNSHFET is designed and its electrical and GIDL characteristics are compared with those of novel devices such as the forksheet FET and complementary FET. [ABSTRACT FROM AUTHOR]

The study focuses on the Vertical Gate-All-Around Multi-Bridge-Channel Field-Effect Transistor (VGAAMBCFET), which is a critical component in developing low-power applications. Several optimization strategies are being investigated to improve VGAA-MBCFET performance, with a particular focus on improving the on-off ratio, reducing leakage current, and fine-tuning I-V characteristics. The study emphasizes the distinctive vertical gate-all around structure and scalability benefits that distinguish VGAA- MBCFETs from horizontal counterparts such as Fin FETs and lateral GAAFETs. In-depth research on the scalability of VGAA-MBCFETs into smaller technological nodes is a significant priority, since it is recognized as crucial to influencing the future of sophisticated and compact integrated circuits. The paper acknowledges these innovations revolutionary impact on large-scale integration (LSI) improvements, as well as their influence on the trajectory of wearable technology within the larger context of integrated circuit miniaturization the issues provided by downsizing are openly discussed, with recognition of their complicated impact on wearable performance and functionality. As wearable technology aims to incorporate high performance computing systems, this study addresses the constraints of traditional techniques and investigates whether VGAA-MBCFETs can be a transformative technology, allowing for compact yet powerful designs in energy efficient electronic gadgets. The study uses robust modelling approaches to provide thorough insights into the capabilities and possible applications of VGAA-MBCFETs, providing a significant contribution to the ongoing progress of low-power electronic device technology. [ABSTRACT FROM AUTHOR]

We report here a study on doping concentration variation on Double Gate Junctionless Field Effect Transistor. Doping concentration for the device is varied from 1010/cm³ to 1019/cm³ and their transfer characteristics and output characteristics were investigated for drain section voltages with 0.1 V, 0.5 V and 1 V. At 1 V drain voltage with doping level 1019 cm-3 a drain current of 1.7 mA has been obtained. Furthermore various electrical parameters like on current, Ion to Iorr ratio, subthreshold swing, threshold voltages are investigated. At 1019 cm and drain potential 1 V current in body is 1.9 mA. On the other hand subthreshold swing obtained at 1019 cm with a drain potential 1 V is 79 mV/Decade. The simulation is done with the help of Cogenda Visual TCAD simulator. By increasing doping concentration better control over drain current can be obtained. Better on current can be achieved at higher doping variation. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Nano- & Electronic Physics is the property of Sumy State University and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

The paper considers the effect of temperature on an optical radiation sensor based on an oscillator with single-junction (SJT) and field-effect (FET) transistors, the output signal of which is the frequency proportional to the radiation intensity. Under the impact of temperature, the parameters of transistors change, causing frequency instability in the temperature. For thermal stabilization of the output signal, a second FET2 with the opposite sign of the current dependence on temperature and adjustable thermal sensitivity is connected in parallel to the first FET1. As a result, the temperature effects of all three transistors on the generation frequency are mutually compensated, and the output frequency is thermally stabilized. [ABSTRACT FROM AUTHOR]

Wafer‐scale deposition of high‐휅 gate dielectrics compatible with atomically thin van der Waals layered semiconductors (e.g., MoS2, WS2, WSe2) is urgently needed for practical applications of field effect transistors based on 2D materials. A study on a high‐휅 molecular crystal antimony trioxide (Sb2O3) gate dielectric examined the role of electrode material on dielectric degradation and breakdown. It is demonstrated that the thin films of Sb2O3 can be uniformly deposited on a wafer scale. The current–voltage (I–V) curves show tightly controlled distributions of both leakage current and breakdown voltage. Electrical measurements reveal that defects are generated gradually upon electrical stressing. The evaluation of degradation is based on charge trapping, stress‐induced leakage current, and dielectric breakdown measurements. The breakdown voltage distribution follows a tight monomodal Weibull distribution suggesting a high quality of the film. Comparing Ti and Au as gate electrodes, both the breakdown field and the tunnel current are affected by the choice of electrode material. Transmission electron microscopy reveals that the chemistry at the electrode/Sb2O3 interface plays an important role and that Ti scavenges oxygen from the Sb2O3, forming a defective oxide layer at the Ti/Sb2O3 interface. For the Au electrode, this interfacial reaction is completely absent, improving the dielectric performance. [ABSTRACT FROM AUTHOR]

High-performance field-effect transistors (FETs) based on atomically thin two-dimensional (2D) semiconductors have demonstrated great promise in post-Moore integrated circuits. However, unipolar p-type 2D semiconductor transistors yet remain challenging and suffer from low saturation current density (less than 10 µA·µm−1) and high contact resistance (larger than 100 kΩ·µm), mainly limited by the Schottky barrier induced by the mismatch of the work-functions and the Fermi level pinning at the metal contact interfaces. Here, we overcome these two obstacles through van der Waals (vdW) integration of high work-function metal palladium (Pd) as the contacts onto monolayer WSe2 grown by chemical vapor deposition (CVD) method. We demonstrate unipolar p-type monolayer WSe2 FETs with superior device performance: room temperature on-state current density exceeding 100 µA·µm−1, contact resistance of 12 kΩ·µm, on/off ratio over 107, and field-effect hole mobility of ~ 103 cm2·V−1·s−1. Electrical transport measurements reveal that the Fermi level pinning effect is completely effectively eliminated in monolayer WSe2 with vdW Pd contacts, leading to a Schottky barrier-free Ohmic contact at the metal-semiconductor junctions. Combining the advantages of large-scale vdW contact strategy and CVD growth, our results pave the way for wafer-scale fabrication of complementary-metal-oxide-semiconductor (CMOS) logic circuits based on atomically thin 2D semiconductors. [ABSTRACT FROM AUTHOR]

Nanofluidic devices have turned out to be exemplary systems for investigating fluidic transport properties in a highly restricted area, where the electrostatic interactions or chemical reactions between nanochannel and flowing species strongly dominate the ions and flow transport. Numerous nanofluidic devices have recently been explored to manipulate ion currents and construct electronic devices. Enlightened by electronic field effect transistors, utilizing the electric field effect of nanopore nanochannels has also been adopted to develop versatile nanofluidic devices. Here, we report a nanopore-based nanofluidic unijunction transistor composed of a conical glass nanopipette with the biomaterial polydopamine (PDA) coated at its outer surface. The asfabricated nanofluidic device exhibited negative differential resistance (NDR) and ion current oscillation (ICO) in ionic transport. The pre-doped copper ions in the PDA moved toward the tip as increasing the potential, having a robust shielding effect on the charge of the tip, thus affecting the surface charge density of the nanopore in the working zone. Finite element simulation based on a continuum model coupled with Stokes-Brinkman and Poisson-Nernst-Planck (PNP) equations revealed that the fluctuations in charge density remarkably affect the transport of ionic current in the nanofluidic device. The as-prepared nanofluidic semiconductor device was a ready-to-use equipment that required no additional external conditions. Our work provides a versatile and convenient way to construct nanofluidic electronic components; we believe by taking advantage of advanced surface modification methods, the oscillation frequency of the unijunction transistors could be controlled on demand, and more nanofluidic devices with resourceful functions would be exploited. [ABSTRACT FROM AUTHOR]

Two-dimensional (2D) dielectrics, integrated with high-mobility semiconductors, show great promise to overcome the scaling limits in miniaturized integrated circuits. However, the 2D dielectrics explored to date still face the challenges of low crystallinity, diminished dielectric constant, and the lack of effective synthesis methods. Here, we report the controllable synthesis of ultra-thin gadolinium oxychloride (GdOCl) nanosheets via a chloride hydrate-assisted chemical vapor deposition (CVD) method. The resultant GdOCl nanosheets display good dielectric properties, including a high dielectric constant (high-κ) of 15.3, robust breakdown field strengths (Ebd) exceeding 9.9 MV/cm, and minimal gate leakage currents of approximately 10−6 A/cm2. The top-gated GdOCl/MoS2 field-effect transistors (FETs) exhibit commendable switch characteristics, a negligible hysteresis of ~5 mV and a subthreshold swing down to 67.9 mV dec−1. The GdOCl/MoS2 FETs can also be employed to construct functional logic gates. Our study underscores the significant potential of the 2D GdOCl dielectric for innovative high-speed operated nanoelectronic devices. van der Waals dielectric materials are required to promote the industrialization of miniaturized 2D electronics. Here, the authors report the growth of GdOCl single crystals with a dielectric constant of 15.3 and equivalent oxide thickness down to 1.3 nm, showing their application for the realization of high-performance 2D MoS2 transistors. [ABSTRACT FROM AUTHOR]

Hysteresis window observed in ferroelectric negative capacitance field-effect transistors (NCFETs) have been a persistent challenge in the development of reliable logic circuits, often leading to abnormal operational conditions. Despite its significance, the underlying factors driving this hysteresis phenomenon remain elusive. In this study, we employ the quasi-static L–K equation in conjunction with the Mott–Gurney law to study the impact of VO++ migration on the hysteresis behavior of NCFETs, based on a surface potential-based physical model. Compared with pristine NCFET, the difference of peak voltages in value of 1.3 V was achieved in VO++-involved sample upon reverse and forwards scanning. This result clearly suggests that the relaxation of charged oxygen vacancies significantly affects the threshold voltage under applied sweeping voltages, providing a plausible explanation for the emergence of hysteresis windows in NCFETs. A replacement of the conventional oxide layer with a buffer layer containing high-mobility ions is proposed to adjust the hysteresis window. Importantly, in accordance with the theoretical predictions, the increased ion mobility results in a substantial reduction in the hysteresis window observed in NCFETs. Our proposed physical mechanism, elucidating the space-charge-induced hysteresis behavior, provides fresh insights for mitigating hysteresis effects, thereby advancing the potential applications of NCFETs in logic circuits. [ABSTRACT FROM AUTHOR]