Search

A 28-GHz voltage-controlled oscillator (VCO) with a wide tuning range and a low phase noise is presented in this paper. A PMOS-only cross-coupled pair with a lower flicker noise is exploited to provide the negative resistance. The mechanisms for enhancing the Q-factor of the LC tank at millimeter-wave (mm-wave) frequencies are analyzed and applied to optimize the proposed VCO design to obtain a low phase noise. To guarantee accurate oscillating frequencies, distributed interconnections are carefully modeled by EM simulations. Fabricated in a standard 90-nm CMOS process, the proposed VCO achieves a wide tuning range of 20.1 %, from 25 to 30.66 GHz and a low phase noise of −105.47 dBc/Hz at 1-MHz offset. The current of the core circuit is 10.5 mA under a single 1.2-V supply. The core area of the chip is 0.38 mm × 0.24 mm.

We present a 31-45.5 GHz injection-locked frequency divider (ILFD) implemented in a standard 90-nm CMOS process. To reduce parasitic capacitance and increase the operating frequency, an NMOS-only cross-coupled pair is adopted to provide negative resistance. Acting as an adjustable resistor, an NMOS transistor with a tunable gate bias voltage is connected to the differential output terminals for locking range extension. Measurements show that the designed ILFD can be fully functional in a wide locking range and provides a good figure-of-merit. Under a 1 V tunable bias voltage, the self-resonant frequency of the divider is 19.11 GHz and the maximum locking range is 37.7% at 38.5 GHz with an input power of 0 dBm. The power con- sumption is 2.88 mW under a supply voltage of 1.2 V. The size of the chip including the pads is 0.62 mm0.42 mm.

A 26–47.9 GHz ultrawideband CMOS dual injection-locked frequency divider (dual-ILFD) with high input impedance is demonstrated. As the differential input signal is injected into the gate of the PMOS tail transistor and NMOS switch transistor, the proposed divider has high input impedance and can be driven easily by the preceding driving circuits. Meanwhile, the locking range of the proposed divider is extended significantly by fully utilizing the dual-injection technique. The proposed dual-ILFD is fabricated in a standard 90-nm CMOS process and on-wafer measurements are performed. The measurements show that the free-running frequency of the divider is 19.11 GHz. At an incident power of 0 dBm, a total locking range from 26 to 47.9 GHz is achieved. The power consumption is 2.88 mW at a supply voltage of 1.2 V. The total chip size is 0.62 × 0.42 mm2. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2126–2129, 2014

A Ka-band sub-harmonically pumped resistive mixer (SHPRM) was designed and fabricated using the standard 0.18-μm complementary metal-oxide-semiconductor (CMOS) technology. An area-effective asymmetric broadside coupled spiral Marchand balance-to-unbalance (balun) with magnitude and phase imbalance compensation is used in the mixer to transform local oscillation (LO) signal from single to differential mode. The results showed that the SHPRM achieves the conversion gain of −15–−12.5 dB at fixed f IF=0.5 GHz with 8 dBm LO input power for the radio frequency (RF) bandwidth of 28–35 GHz. The in-band LO-intermediate freqency (IF), RF-IF, and LO-RF isolations are better than 31, 34, and 36 dB, respectively. Besides, the 2LO-IF and 2LO-RF isolations are better than 60 and 45 dB, respectively. The measured input referred P1dB and 3rd-order inter-modulation intercept point (IIP3) are 0.5 and 10.5 dBm, respectively. The measurement is performed under a gate bias voltage as low as 0.1 V and the whole chip only occupies an area of 0.33 mm2 including pads.

In this paper, a Ka-band Dual-Injection-Locked Frequency Divider (DILFD) using IBM 90-nm CMOS technology is proposed. The dual-injection-locked technique is used to extend the locking range of the frequency dividers based on resonator tank. The injection power is enhanced by fully utilizing the injection of the voltage and current signal. The post layout simulation results show that the locking range of the divide-by-two frequency divider is 7.1 GHz and the input signal frequency is from 30.1 GHz to 37.2 GHz. The whole core circuit draws a DC current of 5.64 mA from a single 1.2-V supply. The chip occupies a layout area of 622µm×585µm.

This paper presents a wide tuning rang mm-wave VCO (voltage controlled oscillator) fabricated in IBM 90-nm CMOS technology. The VCO can be tuned from 31.4 GHz to 42.2 GHz and utilizes a differential tuning mechanism based on varactors and switched capacitors. A switched current source is used to improve the performance of the VCO when an MIM (metal-insulated-metal) capacitor is switched in the LC resonation tank. Without switched capacitor, the VCO core circuit consumes a power of 8.4 mW and exhibits a phase noise of −114 dBc/Hz at 1 MHz offset from resonation frequency, but with switched capacitor, the power is increased to 12.2 mW, and the phase noise is incresed to −104 dBc/Hz.

A 25.4-33.5 GHz wideband CMOS programmable multi-modulus divider with low power consumption is demonstrated. For a high operating frequency and low power consumption, a direct injection-locked frequency divider is used as the prescaler and followed directly by a dual-modulus divided-by-8/9 divider without any driving circuits. The dynamic-loading CML D flip-flips are utilised in the dual-modulus divider which further reduces the power consumption. Implemented in a 90 nm CMOS process, a frequency division from 542 to 654 in steps of 2 is achieved. Measurements show that the self-resonant frequency of the divider is 14.76 GHz, and the locking range is from 25.4 to 33.5 GHz for the total frequency division ratio at an input power of 0 dBm. The power consumption for the maximum division ratio and 0 dBm input power is 15.48 mW at a supply voltage of 1.2 V. The total chip size is 0.72 × 0.47 mm.

A dual-band, wide tuning range voltage-controlled oscillator that uses transformer-based fourth-order (LC) resonator with a compact common-centric layout is presented. Compared with the traditional wide band (VCO), it can double frequency tuning range without degrading phase noise performance. The relationship between the coupling coefficient of the transformer, selection of frequency bands, and the quality factor at each band is investigated. The transformer used in the resonator is a circular asymmetric concentric topology. Compared with conventional octagon spirals, the proposed circular asymmetric concentric transformer results in a higher quality-factor, and hence a lower oscillator phase noise. The VCO is designed and fabricated in a 0.18-μm CMOS technology and has 75% wide tuning range of 3.16–7.01 GHz. Depending on the oscillation frequency, the VCO current consumption is adjusted from 4.9 to 6.3 mA. The measured phase noises at 1 MHz offset from carrier frequencies of 3.1, 4.5, 5.1, and 6.6 GHz are −122.5, −113.3, −110.1, and −116.8 dBc/Hz, respectively. The chip area, including the pads, is 1.2 × 0.62 mm2 and the supply voltage is 1.8 V.

A 30–50 GHz CMOS ultra-wideband (UWB) low-noise amplifier (LNA) with a flat high power gain (S 21), along with a flat low-noise figure (NF) is demonstrated for the Atacama large millimetre array (ALMA) band-1 (31.3–45 GHz) system applications. The high S 21 and low NF are achieved because the triple-well transistors are utilised with their respective source and body terminals connected together. Furthermore, the bandwidth extension and gain flatness is achieved due to the careful design of the inductive-peaking networks. The LNA has a measured S 21 of 21.5 ± 1.5 dB, a minimum NF (NFmin) of 3.8 dB at 32.5 GHz, an average NF (NFavg) of 4.67 dB over the range of 30–50 GHz and an input third-order intercept point (IIP3) of 0 dBm, with a DC power consumption of 20.4 mW at 1.2 V supply. The proposed LNA outperforms all the reported commercial standard CMOS Q-band LNAs, with the highest gain bandwidth product and highest IIP3 suitable for the ALMA band-1 system applications.