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Polar code is a breakthrough in coding theory. Using list successive cancellation decoding with large list size L, polar codes can achieve excellent error correction performance. The L partial decoded vectors are stored in the path memory and updated according to the results of list management. In the state-of-the-art designs, the memories are implemented with registers and a large crossbar is used for copying the partial decoded vectors from one block of memory to another during the update. The architectures are quite area-costly when the code length and list size are large. To solve this problem, we propose two optimization schemes for the path memory in this work. First, a folded path memory architecture is presented to reduce the area cost. Second, we show a scheme that the path memory can be totally removed from the architecture. Experimental results show that these schemes effectively reduce the area of path memory.

Polar codes are the first class of forward error correction (FEC) codes with a provably capacity-achieving capability. Using list successive cancellation decoding (LSCD) with a large list size, the error correction performance of polar codes exceeds other well-known FEC codes. However, the hardware complexity of LSCD rapidly increases with the list size, which incurs high usage of the resources on the field programmable gate array (FPGA) and significantly impedes the practical deployment of polar codes. To alleviate the high complexity, in this paper, two low-complexity decoding schemes and the corresponding architectures for LSCD targeting FPGA implementation are proposed. The architecture is implemented in an Altera Stratix V FPGA. Measurement results show that, even with a list size of 32, the architecture is able to decode a codeword of 4096-bit polar code within 150 μs, achieving a throughput of 27Mbps. © 2017 Ghent University.

Owing to their capacity-achieving performance and low encoding and decoding complexity, polar codes have received significant attention recently. Successive cancellation decoding (SCD) and belief propagation decoding (BPD) are two popular approaches for decoding polar codes. SCD, despite having less computational complexity when compared with BPD, suffers from long latency due to the serial nature of the SC algorithm. BPD, on the other hand, is parallel in nature and is more attractive for low-latency applications. However, due to the iterative nature of BPD, the required latency and energy dissipation increase linearly with the number of iterations. In this paper, we propose a novel scheme based on subfactor-graph freezing to reduce the average number of computations as well as the average number of iterations required by BPD, which directly translates into lower latency and energy dissipation. Simulation results show that the proposed scheme has no performance degradation and achieves significant reduction in computation complexity over the existing methods. Moreover, the hardware architecture for the proposed scheme is developed and compared with the state-of-the-art BPD implementations for (1024, 512) polar codes. A decoding throughput of 13.9 Gb/s is achieved along with a 60%-73% improvement in energy reduction and two times increase in hardware efficiency when compared with the existing BPD implementations. © 2016 IEEE.

The performance of List Successive-Cancellation Decoding (LSCD) of Polar Codes with large list size have exceeded that of Turbo codes and Low-Density Parity-Check codes. However, large list size results in huge computation complexity and this limits the applicability of LSCD in high-throughput and power- sensitive applications. In this work, a low complexity design for LSCD with large list size based on list pruning is proposed. In particular, the property of the relative path metric (RPM) of each list candidate with respect to that of the most-likely candidate is investigated. It is found that the correct candidate has a low possibility of having a large value of RPM and based on this property, a list pruning method and the corresponding low-complexity LSCDs are proposed. From the simulation results, as compared to the conventional LSCD, the proposed LSCDs have negligible performance loss while the computation complexity is reduced by more than 80%. In addition, the proposed design is hardware-friendly and easily adaptable to the existing LSCDs hardware architectures. © 2016 IEEE.

Due to their provably capacity-achieving performance, polar codes have attracted a lot of research interest recently. For a good error-correcting performance, list successive-cancellation decoding (LSCD) with large list size is used to decode polar codes. However, as the complexity and delay of the list management operation rapidly increase with the list size, the overall latency of LSCD becomes large and limits the applicability of polar codes in high-throughput and latency-sensitive applications. Therefore, in this work, the low-latency implementation for LSCD with large list size is studied. Specifically, at the system level, a selective expansion method is proposed such that some of the reliable bits are not expanded to reduce the computation and latency. At the algorithmic level, a double thresholding scheme is proposed as a fast approximate-sorting method for the list management operation to reduce the LSCD latency for large list size. A VLSI architecture of the LSCD implementing the selective expansion and double thresholding scheme is then developed, and implemented using a UMC 90 nm CMOS technology. Experimental results show that, even for a large list size of 16, the proposed LSCD achieves a decoding throughput of 460 Mbps at a clock frequency of 658 MHz.

Throughput and complexity are the important criteria of the Very-Large-Scale Integration (VLSI) implementation of the modern high-performance wireless communication system. In this work, the high-throughput low-complexity digital baseband architecture is studied for high-performance wireless data path. In particular, the hardware implementation is optimized with a methodology of the algorithm-and-architecture co-design. The following modules of a bandwidth-efficient communication system are investigated: the demapper for multi-ary constellation, the successive cancellation decoding for polar codes, and the list decoding for polar codes. For constellation demapper, several low-complexity demappers are proposed for the rotated quadrature amplitude modulation constellation used in the Digital Video Broadcasting – Second Generation Terrestrial standard. The demapping complexity is reduced by approximating the 2-dimensional detection with 1-dimensional detection and compensating the loss due to the correlation between the in-phase and quadrature components. Experimental results show that the demapping complexity is reduced by more than 50% with the proposed demappers when comparing with the optimal demapper, while the performance degradation is negligible. For the successive cancellation decoding (SCD) of the polar codes, both high-throughput and low-cost architectures are proposed. First, a new partial-sum updating algorithm and the corresponding partial-sum network (PSN) architecture are introduced which achieve a delay performance independent of the code length. Second, for a high-performance and area-efficient semi-parallel SCD implementation, a folded PSN architecture is presented to integrate seamlessly with the folded processing element architecture. As a result, both the critical path delay and the area (excluding the memory for folding) of the semi-parallel SCD are approximately constant for a large range of code lengths. The proposed designs are implemented in

Bit-interleaved coded modulation with iterative decoding has been widely adopted in modern wireless communication systems because of its spectral efficiency and low detection complexity. Because of the iterative decoding structure, the overall decoding latency depends on the latency of both the demapper and the channel decoder. In this work, a parallel demapper architecture is proposed for a low latency implementation. Two look-ahead techniques are proposed to further reduce the latency of the parallel architecture. Techniques exploiting the symmetry property of the labeling and the common terms of the look-ahead pre-calculation are also presented to reduce the computation complexity overhead of the proposed architecture. Implementation results show that the latency is reduced by 40% when comparing with traditional sequential demapper architecture. © 2014 IEEE.

Polar codes have recently received a lot of attention because of their capacity-achieving performance and low encoding and decoding complexity. The performance of the successive cancellation decoder (SCD) of the polar codes highly depends on that of the partial-sum network (PSN) implementation. Hence, in this work, an efficient PSN architecture is proposed, based on the properties of polar codes. First, a new partial-sum updating algorithm and the corresponding PSN architecture are introduced which achieve a delay performance independent of the code length. Moreover, the area complexity is also reduced. Second, for a high-performance and area-efficient semi-parallel SCD implementation, a folded PSN architecture is presented to integrate seamlessly with the folded processing element architecture. This is achieved by using a novel folded decoding schedule. As a result, both the critical path delay and the area (excluding the memory for folding) of the semi-parallel SCD are approximately constant for a large range of code lengths. The proposed designs are implemented in both FPGA and ASIC and compared with the existing designs. Experimental result shows that for polar codes with large code length, the decoding throughput is improved by more than 1.05 times and the area is reduced by as much as 50.4%, compared with the state-of-the-art designs.

To support simultaneous multicasting and unicasting service, a 2-level superposition coded modulation (SCM) system with variable code rate allocation is studied. To obtain the most power-efficient scheme for this system, brute-force method can be used to find the best power allocation for each code rate allocation. However, it is very complicated and time-consuming. In this work, the properties of the 2-level SCM capacity is first studied using numerical evaluation and a heuristic method is proposed to efficiently find the optimal rate assignment and power allocation. The simulation results verify the performance of the proposed power allocation method and experimental results show that equal rate allocation scheme provides a power-efficient transmission.

Gray mapping and signal space diversity (SSD) are adopted in DVB-T2 to achieve better performance and system robustness. However, the traditional maximum a posteriori demapping for Gray mapped SSD signal is complicated for higher order modulation and it is not practical to be used in the iterative receiver structure. In this work, simplified demappers are proposed by approximating the 2-dimensional detection with 1-dimensional detection and compensating the loss due to the correlation between the I and Q components. Simulation results show that the proposed simplified demappers can approach the optimal demapper performance with a much lower complexity.

Multi-level superposition coded modulation (SCM) is a scalable technique for wireless video broadcast/ multicast, in which iterative turbo structures provide receivers with multi-resolution demodulations subject to a high complexity. Forward error correction using low-density parity-check (LDPC) code is helpful for better received video quality but further increasing the receiver complexity. In this paper, a method is proposed to reduce the receiver complexity by using a sequential structure with a faster convergence for demodulation. In addition, the iterative demodulator and the LDPC decoder are jointly designed as a multi-loop iterative structure to reduce the decoding complexity. Experimental results show that up to 67% decoding complexity is reduced and better video quality is achieved at receivers under low signal-to-noise ratios. © 2011 IEEE.