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Neural networks are widely used in critical environments such as healthcare, autonomous vehicles, or video surveillance. To ensure the safety of the systems that rely on their functionality, it is essential to validate their correct behaviour in the presence of faults. This paper studies the behaviour of state-of-the-art neural network models with fault injection in their weights. For this purpose, we analyse the sensitivity of these models and identify the impact of bit flips on their accuracy. To mitigate the effects of faults, we introduce two mechanisms that leverage bit-level redundancy for protection. The first mechanism, Fixed Protection, safeguards consecutive sets of bits, while the second, Variable Protection, targets non-consecutive bits. Our findings demonstrate that, on average, random bit flip faults cause the accuracy of the original models to drop by 1.3% to over 3%. However, with our protection mechanisms in place, accuracy reductions are significantly minimised, ranging from only 0.0001% to 0.4%. [ABSTRACT FROM AUTHOR]

Complementary Metal-Oxide-Semiconductor (CMOS) image sensors (CISs), known for their high integration, low cost, and superior performance, have found widespread applications in satellite and space exploration. However, the readout circuits of pixel arrays are vulnerable to functional failures in complex or intense radiation environments, particularly due to transient γ radiation. Using Technology Computer-Aided Design (TCAD) device simulations and Simulation Program with Integrated Circuit Emphasis (SPICE) circuit simulations, combined with a double-exponential current source fault injection method, this study investigates the transient dose rate effect (TDRE) on a typical readout circuit of CISs. It presents the variations in the photoelectric signal under different dose rates and at different occurrence moments of the TDRE. The results show that, under low dose rates, the CIS readout circuit can still perform data acquisition and digital processing, with the photoelectric signal exhibiting some sensitivity to the occurrence moment. At high dose rates, however, the photoelectric signal not only remains sensitive to the occurrence moment but also shows significant discreteness. Further analysis of the CIS readout circuit sequence suggests that the occurrence moment is a critical factor affecting the circuit's performance and should not be overlooked. These findings provide valuable insights and references for further research on the TDRE in circuits. [ABSTRACT FROM AUTHOR]

Deep neural networks (DNNs) have been applied across diverse domains, including safety-critical applications. Past studies indicate that DNNs are very sensitive to changes in weights and activations due to uneven bit-weight distribution in standard number formats like fixed points, which can cause significant output accuracy fluctuations. To address this issue, we introduce a new data type called MONO to enhance bit-flip resilience using uniformity at the bit level by employing symmetric weights for all bit positions. On average, MONO has improved error resilience more effectively than the fixed-point data type, even when utilizing triple modular redundancy (TMR) and most significant bit (MSB) protection, while maintaining low overhead. [ABSTRACT FROM AUTHOR]

Neural network object detectors are increasingly being used for aerial video analysis, with a growing demand for onboard processing on UAVs and other limited resources. However, the vulnerability of neural networks to adversarial noise, out-of-distribution data, and fault injections reduces the functionality and reliability of these solutions. The development of detector models and training methods that simultaneously ensure computational efficiency and robustness against disturbances is an urgent scientific task. The research subjects. The model and method for ensuring the robustness of resource-constrained neural network systems for object detection in aerial video surveillance. Objective. Development of a model and method to ensure the robustness of object detectors for aerial image analysis. Methods. Combination of ideas and methods for dynamic neural networks, and methods for robustness and resilience optimization for neural networks. Results. The detector model with a ViT-B/16 backbone modified with gate units for dynamic inference was developed. The model was trained on the VEDAI dataset and meta-trained on the results of adaptation to different types of disturbances. The model with different training methods was tested for robustness against random bit-flip injection where the proportion of the modified weights is determined at a fault rate of 0.1. In addition, the model with different training methods were tested for robustness against a black-box Adversarial Attack with a perturbation level of 3/255 according to the L¥ norm. Conclusions. The object detection model for aerial images with dynamic inference and optimized robustness is developed for the first time. The model includes a transformer-based backbone, gate units, and simplified feature pyramid network with a RetinaNet detection head. Gate units are trained to deactivate transformer encoders that are irrelevant to the input data and disturbances. The proposed model reduces FLOPs by more than 22% without loss of mean Average Precision (mAP) by deactivating some encoders. The detector training method was developed for the first time, combined the RetinaNet loss function with the gate unit loss function and applied meta-learning to the results of adaptation to various types of synthetic disturbances. The analysis of the experimental results demonstrates that the proposed method provides an 11.7 % increase in mAP during testing under fault injection conditions and a 15.1 % increase in mAP during adversarial attack testing.

As a critical component of electric vehicles, the powertrain has a significant impact on the overall performance of vehicles. In addressing the challenge of lengthy testing cycles, this study develops a para model of the powertrain, utilizing digital twin (DT) technology, thereby establishing a framework for simulation testing of multi-controller intermodulation. We establish functional definition coverage testing by designing specific functional requirement use cases, and we validate the failure mechanism via fault injection use cases. The results indicate that the DT testing platform can effectively simulate the operational interactions among various controllers within the powertrain system. In comparison to traditional field testing, the digital twin-based testing methodology offers enhanced operational efficiency and allows for the examination of testing conditions that are impractical to implement in real vehicles, particularly in the context of fault injection testing, thus facilitating the early detection of potential safety risks within the system. The advancement of this technical solution holds significant practical implications for the future mass production and development of electric vehicles. [ABSTRACT FROM AUTHOR]

Artificial intelligence technologies are becoming increasingly prevalent in resource-constrained, safety-critical embedded systems. Numerous methods exist to enhance the resilience of AI systems against disruptive influences. However, when resources are limited, ensuring cost-effective resilience becomes crucial. A promising approach for reducing the resource consumption of AI systems during test-time involves applying the concepts and methods of dynamic neural networks. Nevertheless, the resilience of dynamic neural networks against various disturbances remains underexplored. This paper proposes a model architecture and training method that integrate dynamic neural networks with a focus on resilience. Compared to conventional training methods, the proposed approach yields a 24% increase in the resilience of convolutional networks and a 19.7% increase in the resilience of visual transformers under fault injections. Additionally, it results in a 16.9% increase in the resilience of convolutional network ResNet-110 and a 21.6% increase in the resilience of visual transformer DeiT-S under adversarial attacks, while saving more than 30% of computational resources. Meta-training the neural network model improves resilience to task changes by an average of 22%, while achieving the same level of resource savings. [ABSTRACT FROM AUTHOR]

The performance of electrical connectors can be significantly impacted by periodic variations in contact resistance caused by vibrational stress. Intermittent faults resulting from such stress are characterized by their random and fleeting nature, making it difficult to study and replicate them. This paper proposes a novel method for reproducing intermittent faults in electrical connectors. To implement this method, intermittent fault data are first collected from electrical connectors subjected to different vibration loads. Next, a statistical distribution model is constructed using kernel density estimation (KDE). Based on this model, a fault injector is designed to simulate intermittent faults under varying vibration loads. The simulated faults are then compared to real-world intermittent fault signals in a controlled environment to validate the accuracy of the method. The results demonstrate that the proposed method effectively reproduces intermittent faults in electrical connectors under varying vibration conditions. This approach can be used to better understand the behavior of connectors under vibrational stress and to develop more effective testing and fault diagnosis methods. [ABSTRACT FROM AUTHOR]

Evaluating program reliability against software faults involves the work of analyzing program failure against software faults as behavior on failures is fundamental for assessing reliability. Similar failure behavior reflects similar reliability assessment against software faults of same time–space distribution. Since program failure is determined by fault manifestations, working on similarities on fault manifestations helps figuring out failures in similarity as well. In this paper, we propose a novel method to characterize program behavior by defining fine-grained runtime states at assembly-level of code, aiming to capture the very first abnormal manifestation—first-error—after software fault being activated during program run. Failure prediction model and measurement is presented based on similarities reflected by the runtime behaviors obtained. Fault injection experiments are conducted to verify the prediction measurement by utilizing software faults of Orthogonal Defect Classification to inject and MiBench programs to perform. Over 15 000+ times of fault injection by considering type and location of fault were conducted into each program in order to quantify and analyze the sensitivity on first-error and similarity on failure accordingly. The results show that programs having particular structural features (e.g. massive operations with regards to calculations, nested function-calls, case structures and loop structures, etc.) are well characterized toward first-error behaviors by extracting fine-grained states. Similarities on first-error sensitivity can be represented better for these programs as well. Same trend is seen on failure behavior and its prediction measurement. [ABSTRACT FROM AUTHOR]

Simulation-based Fault Injection (FI) is crucial for validating system behaviour in safety-critical applications, such as the automotive industry. The ISO 26262 standard's Part 11 extension provides failure modes for digital components, driving the development of new fault models to assess software-implemented mechanisms against random hardware failures (RHF). This paper proposes a Fault Injection framework, QEFIRA, and shows its ability to achieve the failure modes proposed by Part 11 of the ISO 26262 standard and estimate relevant metrics for safety mechanisms. QEFIRA uses QEMU to inject permanent and transient faults during runtime, whilst logging the system state and providing automatic post-execution analysis. Complemented with a confusion matrix, it allows us to gather standard compliant metrics to characterise and evaluate different designs in the early stages of development. Comparatively to the native QEMU implementation, the tool only shows a slowdown of 1.4 × for real-time microcontroller-based applications. [ABSTRACT FROM AUTHOR]

One of the most popular models that provide computer resources today is cloud computing. Today's dynamic and successful platforms are created to take advantage of various resources available from service providers. Ensuring the performance and availability of such resources and services is a crucial problem. Any software system may be subject to faults that might propagate to cause failures. Such faults with the potential of contributing to failures are critical because they impair performance and result in a delayed reaction, which is regarded as a dependability problem. To ensure that critical faults can be discovered as soon as possible, the impact of such faults on the system must be tested. The performance and dependability of cloud-native systems are examined in this empirical study using fault injection, one of the chaos engineering techniques. The study explores the impacts and results of injecting various delay times into two cloud-native applications with diverse user numbers. The performance of the applications with various numbers of users is measured in relation to these delays, which accordingly reflects measuring the dependability of those systems. Firstly, the systems' architecture were identified, and serverless with two Lambda functions and containerised microservices applications were chosen, which depend on utilising and incorporating cloud-native services. Secondly, faults are injected in order to quantify performance attributes such as throughput and latency. The results of several controlled experiments carried out in real-world cloud environments provide exploratory empirical data, which promoted comparisons and statistical analysis that we utilised to identify the behaviour of the application while experiencing stress. Typical results from this investigation include an overall reduction in performance that is embodied in an increase in latency with injecting delays. However, a remarkable result is noticed at a particular delay in which defects and availability problems appear out of nowhere. These findings assist in highlighting the value of using chaos engineering in general and fault injection in particular to assess the dependability of cloud-native applications and to find unpredicted failures that could arise quickly from defects that aren't supposed to spread and result in dependability issues. [ABSTRACT FROM AUTHOR]

EM(Electromagnetic) fault injection requires finding parameters such as timing, intensity, and location to cause the intended fault. Previously, iterative EM fault-injection experiments were conducted to determine the parameters that cause the intended error. However, this is time consuming and requires the replacement of several target devices owing to permanent faults during the experiment. This study identifies the location of vulnerable circuits from the EM emitted when the target algorithm is operating and analyzes their relationship with the EM fault injection. The proposed methods apply to three different attacker assumptions: differential analysis of the EM intensity, correlation analysis of the power and EM, and correlation analysis of the EM and the intermediate value of the cipher. In our validation, all the proposed methods consistently identified a specific region of the chip as the key location. The results of several experiments in which the timing and intensity parameters of the actual EM fault injection are changed also indicate the vulnerability of the same region, proving the validity of the proposed method. The methods proposed in this study are experimentally proven to exclude at least 75% of the chip area from the EM fault injection location searches through experiments conducted on XMEGA128D4. [ABSTRACT FROM AUTHOR]

Neural network object detectors are increasingly being used for aerial video analysis, with a growing demand for onboard processing on UAVs and other limited resources. However, the vulnerability of neural networks to adversarial noise, out-of-distribution data, and fault injections reduces the functionality and reliability of these solutions. The development of detector models and training methods that simultaneously ensure computational efficiency and robustness against disturbances is an urgent scientific task. The research subjects. The model and method for ensuring the robustness of resource-constrained neural network systems for object detection in aerial video surveillance. Objective. Development of a model and method to ensure the robustness of object detectors for aerial image analysis. Methods. Combination of ideas and methods for dynamic neural networks, and methods for robustness and resilience optimization for neural networks. Results. The detector model with a ViT-B/16 backbone modified with gate units for dynamic inference was developed. The model was trained on the VEDAI dataset and meta-trained on the results of adaptation to different types of disturbances. The model with different training methods was tested for robustness against random bit-flip injection where the proportion of the modified weights is determined at a fault rate of 0.1. In addition, the model with different training methods were tested for robustness against a black-box Adversarial Attack with a perturbation level of 3/255 according to the L norm. Conclusions. The object detection model for aerial images with dynamic inference and optimized robustness is developed for the first time. The model includes a transformer-based backbone, gate units, and simplified feature pyramid network with a RetinaNet detection head. Gate units are trained to deactivate transformer encoders that are irrelevant to the input data and disturbances. The proposed model reduces FLOPs by more than 22% without loss of mean Average Precision (mAP) by deactivating some encoders. The detector training method was developed for the first time, combined the RetinaNet loss function with the gate unit loss function and applied meta-learning to the results of adaptation to various types of synthetic disturbances. The analysis of the experimental results demonstrates that the proposed method provides an 11.7 % increase in mAP during testing under fault injection conditions and a 15.1 % increase in mAP during adversarial attack testing. [ABSTRACT FROM AUTHOR]

To validate safety-related automotive software systems, experimental tests are conducted at different stages of the V-model, which are referred as "X-in-the-loop (XIL) methods". However, these methods have significant drawbacks in terms of cost, time, effort and effectiveness. In this study, based on hardware-in-the-loop (HIL) simulation and real-time fault injection (FI), a novel testing framework has been developed to validate system performance under critical abnormal situations during the development process. The developed framework provides an approach for the real-time analysis of system behavior under single and simultaneous sensor/actuator-related faults during virtual test drives without modeling effort for fault mode simulations. Unlike traditional methods, the faults are injected programmatically and the system architecture is ensured without modification to meet the real-time constraints. Moreover, a virtual environment is modeled with various environmental conditions, such as weather, traffic and roads. The validation results demonstrate the effectiveness of the proposed framework in a variety of driving scenarios. The evaluation results demonstrate that the system behavior via HIL simulation has a high accuracy compared to the non-real-time simulation method with an average relative error of 2.52. The comparative study with the state-of-the-art methods indicates that the proposed approach exhibits superior accuracy and capability. This, in turn, provides a safe, reliable and realistic environment for the real-time validation of complex automotive systems at a low cost, with minimal time and effort. [ABSTRACT FROM AUTHOR]

Graphics processing units (GPUs) have become integral to embedded systems and supercomputing centres due to their large memory, cutting-edge technology and high performance per watt. However, their susceptibility to transient errors requires a comprehensive analysis of error sensitivity, as well as the development of error mitigation techniques and fault-tolerant algorithms. This study focuses on evaluating the soft-error sensitivity of two distinct versions of LU decomposition algorithms implemented on two very different GPUs—a low-power SoC embedded GPU and a high-performance massively parallel GPU. Through extensive fault injection campaigns on both GPUs, we examine the vulnerability of the algorithms, identify error causes, and determine critical code components requiring enhanced protection. The experiments reveal that most single bit flip fault injections in the instruction results lead to erroneous outcomes or unrecoverable errors. Notably, efficient GPU resource utilisation can increase the number of masked errors, thereby enhancing error resilience. Additionally, while different parts of the code exhibit similar error occurrence types and rates, the propagation of errors to elements within the result matrix differs significantly. [ABSTRACT FROM AUTHOR]

Modern multicore processors use network-on-chip (NoC) as the communication backbone. With aggressive product release deadlines due to competition from peers, the usage of third-party intellectual property (IP) blocks for NoCs is a common practice. Hardware Trojans in NoC can lead to performance degradation and the exposure of sensitive information through data leakage. We address this problem by devising a secure, lightweight cryptosystem called secure NoC (Sec-NoC) to be used for on-chip communications, ensuring confidentiality and integrity. The Sec-NoC implements authenticated packet encryption as well as an integrity check at network interfaces. The recovery from faults is facilitated by injecting NACKs and retransmissions into the network. Unlike the existing works, a key-encapsulation method is also discussed for sharing the symmetric key between two nodes. Experimental results show that the Sec-NoC experiences a latency overhead of 1.3% only with minimal area and power overhead. [ABSTRACT FROM AUTHOR]

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Hardware faults are a known source of security vulnerabilities. Fault injection in secure embedded systems leads to information leakage and privilege escalation, and countless fault attacks have been demonstrated both in simulation and in practice. However, there is a significant gap between simulated fault attacks and physical fault attacks. Simulations use idealized fault models such as single-bit flips with uniform distribution. These ideal fault models may not hold in practice. On the other hand, practical experiments lack the white-box visibility necessary to determine the true nature of the fault, leading to probabilistic vulnerability assessments and unexplained results. In embedded software, this problem is further exacerbated by the layered abstractions between the hardware (where the fault originates) and the application software (where the fault effect is observed). We present FaultDetective, a method to investigate the root-cause of fault injection from fault detection in software. Our main insight is that fault detection in software is only the end-point of a chain of events that starts with a fault manifestation in hardware and propagates through the micro-architecture and architecture before reaching the software level. To understand the fault effects at the hardware level, we use a scan chain, a low-level hardware test structure. We then use white-box simulation to propagate and observe hardware faults in the embedded software. We efficiently visualize the fault propagation across abstraction levels using a hash-tree representation of the scan chain. We implement this concept in a multi-core MSP430 micro-controller that redundantly executes an application in lock-step. With this setup, we observe the fault effects for several different stressors, including clock glitching and thermal laser stimulation, and explain the root-cause in each case.

Fault injection attacks represent a type of active, physical attack against cryptographic circuits. Various countermeasures have been proposed to thwart such attacks, however, the design and implementation of which are intricate, error-prone, and laborious. The current formal fault-resistance verification approaches are limited in efficiency and scalability. In this paper, we formalize the fault-resistance verification problem and show that it is coNP-complete. We then devise a novel approach for encoding the fault-resistance verification problem as the Boolean satisfiability (SAT) problem so that modern off-the-shelf SAT solvers can be utilized. The approach is implemented in an open-source tool FIRMER which is evaluated extensively on realistic cryptographic circuit benchmarks. The experimental results show that FIRMER is able to verify fault-resistance of almost all (72/76) benchmarks in 3 minutes (the other three are verified in 35 minutes and the hardest one is verified in 4 hours). In contrast, the prior approach fails on 31 fault-resistance verification tasks even after 24 hours (per task).

Günümüzde, gelişen görüntü işleme teknikleri ile birlikte kamera tabanlı robotik inceleme sistemleri oldukça popülerlik kazanmıştır. Bu tür sistemler gıdadan, askeriyeye birçok sektörde yoğun olarak kullanılmaktadır. Bu sistemler geliştirilirken gerekli olan doğrulama ve onaylama süreçleri oldukça uzun ve maliyetli olmaktadır. Bu çalışma, kamera tabanlı endüstriyel robotik sistemler üzerinde doğrulama ve onaylama faaliyetlerini gerçekleştirmek ve iyileştirmek amacıyla geliştirilmiştir. RGB ve TOF kameralara farklı türlerde (Open, Close, Dilation, Erosion, Gradient, Motionblur, Tuz&Biber, Gaussian ve Poisson) hata enjeksiyon yöntemleri kullanılmasını mümkün Kamera Hata Enjeksiyon Aracı (CamFITool) ile gerçekleştirilmiş testler ve sonuçlar açıklanmıştır. Yapılan çalışma, VALU3S projesi kapsamında, OTOKAR’ın ROKOS robotik sistemine, CamFITool ile gerçek ortamdan alınmış kamera görüntülerinden oluşan kitaplıklara, çeşitli konfigürasyonlarda hatalar enjekte edilip, bu enjeksiyonun sisteme etkilerinin incelenmesine odaklanmıştır. Bu kapsamda 49 farklı test komfigürasyonunda hata enjeksiyonu gerçekleştirilmiştir. Sonuç olarak, kamera tabanlı endüstriyel robotik sistemlerin daha güvenli ve stabil çalışmalarının sağlanması için, bu sistemlerin hataya dayanıklı olup olmadıklarını test eden açık kaynaklı bir hata enjeksiyon aracı olan CamFITool önerilmiştir.

Complementary Metal-Oxide-Semiconductor (CMOS) image sensors (CISs), known for their high integration, low cost, and superior performance, have found widespread applications in satellite and space exploration. However, the readout circuits of pixel arrays are vulnerable to functional failures in complex or intense radiation environments, particularly due to transient γ radiation. Using Technology Computer-Aided Design (TCAD) device simulations and Simulation Program with Integrated Circuit Emphasis (SPICE) circuit simulations, combined with a double-exponential current source fault injection method, this study investigates the transient dose rate effect (TDRE) on a typical readout circuit of CISs. It presents the variations in the photoelectric signal under different dose rates and at different occurrence moments of the TDRE. The results show that, under low dose rates, the CIS readout circuit can still perform data acquisition and digital processing, with the photoelectric signal exhibiting some sensitivity to the occurrence moment. At high dose rates, however, the photoelectric signal not only remains sensitive to the occurrence moment but also shows significant discreteness. Further analysis of the CIS readout circuit sequence suggests that the occurrence moment is a critical factor affecting the circuit’s performance and should not be overlooked. These findings provide valuable insights and references for further research on the TDRE in circuits.

Approximate Computing (AxC) aims at optimizing the hardware resources in terms of area and power consumption at the cost of a reasonable degradation in computation accuracy. Several design exploration approaches and metrics have been proposed so far to identify the approximation targets, but only a few of them exploit information derived from assertion-based verification (ABV). In this paper we propose an ABV methodology to guide the AxC design exploration of RTL descriptions; we consider two main approximation techniques: bit-width and statement reduction. Assertions are automatically mined from the simulation traces of the original design to capture the golden behaviours. Then, we consider the syntactic and semantic aspects of the assertions to rank the approximation targets. The proposed methodology generates a list of statements sorted by their increasing impact on altering the functional correctness of the original design, when selected to be approximated. Through experiments on a case study, we show that the proposed approach represents a promising solution toward the automation of AxC design exploration at RTL. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Shanghai University of Engineering Science / Shanghai Gongcheng Jishu Daxue Xuebao is the property of Journal of Shanghai University of Engineering Science Editorial Office and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

High-Performance Computing (HPC) systems are designed for large-scale processing and complex dataset analysis leveraging scalability, efficiency, and parallelism, often integrating specialized hardware structures such as Vector Processing Units (VPUs). As these systems have grown in complexity and scale, their vulnerability to errors and failures has become an important and complex issue in the HPC world. Our research addresses this challenge by exploring and implementing advanced fault tolerance techniques inside the Vitruvius+ architecture, a partial out-of-order Vector Processing Unit. To the best of our knowledge, this is the first full RTL-level implementation of instruction replication in an HPC-class vector processor for reliability. Specifically, we investigate the integration and interaction of redundancy mechanisms inside the most sensitive architectural units, obtaining a reduction of 75% in non-silent faults causing system failure, proven by an extensive fault injection simulation campaign, with a hardware overhead of only 7.5% and a negligible variation in clock frequency.

With the rapid advancement of quantitative trading technology, the demand for low-latency in Level 2 Deep Market Quote (L2DMQ) Decoding is ever-increasing. The L2DMQ decoder faces increasingly significant challenges in terms of bandwidth and performance. As a result, L2DMQ decoders based on FPGA and ASIC technologies are becoming mainstream solutions. Functional verification and testing of L2DMQ decoders implemented as digital circuits became a challenging task. Given the richness of message template types in L2DMQ and the expanded functionalities of decoders potentially leading to decreased stability in the verification platform, efficient and stable decoder functional verification becomes a complex issue. Furthermore, factors like long-term operation or environments with increased levels of electrostatic electricity or charged particle occurrences can lead to functional faults in the decoding circuit. Thus, error injection has become critically important for testing the reliability of the L2DMQ decoder. This paper investigates the encoding method of L2DMQ, providing a comprehensive complexity analysis. Based on the analysis, a message-template-based (MTB) random stimulus generation method is proposed. Compared to the traditional Message-Length-based (MLB) random stimulus generation method, our proposed MTB method simplifies the reference model of the verification platform and enhances its stability. The experimental results show that the verification platform reduces runtime by 26.69% to 69.29%. Building on this, we target a Universal Verification Methodology (UVM)-based fault-injection and detection platform with MTB random stimulus. Experimental results reveal that the obtained functional coverage reaches up to more than 99% when the number of fault injections ranges from 3750 to 22500. This demonstrates the efficiency of the proposed techniques when adopted using UVM and determines error severity levels through the functional coverage while varying different MTB random stimuli.

Quanvolutional neural networks (QNNs) have been successful in image classification, exploiting inherent quantum capabilities to improve performance of traditional convolution. Unfortunately, the qubit's reliability can be a significant issue for QNNs inference, since its logical state can be altered by both intrinsic noise and by the interaction with natural radiation. In this article, we aim at investigating the propagation of logical-shift errors (i.e., the unexpected modification of the qubit state) in QNNs. We propose a bottom–up evaluation reporting data from 13 322 547 200 logical-shift injections. We characterize the error propagation in the quantum circuit implementing a single convolution and then in various designs of the same QNN, varying the dataset and the network depth. We track the logical-shift error propagation through the qubits, channels, and subgrids, identifying the faults that are more likely to cause misclassifications. We found that up to 10% of the injections in the quanvolutional layer cause misclassification and even logical-shifts of small magnitude can be sufficient to disturb the network functionality. Our detailed analysis shows that corruptions in the qubits' state that alter their probability amplitude are more critical than the ones altering their phase, that some object classes are more likely than others to be corrupted, that the criticality of subgrids depends on the dataset, and that the control qubits, once corrupted, are more likely to modify the QNN output than the target qubits.

Artificial intelligence technologies are becoming increasingly prevalent in resource-constrained, safety-critical embedded systems. Numerous methods exist to enhance the resilience of AI systems against disruptive influences. However, when resources are limited, ensuring cost-effective resilience becomes crucial. A promising approach for reducing the resource consumption of AI systems during test-time involves applying the concepts and methods of dynamic neural networks. Nevertheless, the resilience of dynamic neural networks against various disturbances remains underexplored. This paper proposes a model architecture and training method that integrate dynamic neural networks with a focus on resilience. Compared to conventional training methods, the proposed approach yields a 24% increase in the resilience of convolutional networks and a 19.7% increase in the resilience of visual transformers under fault injections. Additionally, it results in a 16.9% increase in the resilience of convolutional network ResNet-110 and a 21.6% increase in the resilience of visual transformer DeiT-S under adversarial attacks, while saving more than 30% of computational resources. Meta-training the neural network model improves resilience to task changes by an average of 22%, while achieving the same level of resource savings.

Ensuring the safety, security, robustness, and fault tolerance of advanced robotic systems is essential for various fields, including healthcare, industry, and space. To address these issues, it is necessary to use software testing techniques and standards, similar to those applied in other safety-critical applications. The Robot Operating System (ROS) is a popular choice for developing robotic systems, so it is important to have specialized testing libraries and methods for it. In this study, a novel mutation testing library for ROS was developed and integrated it into the automated/tailored mutation-based software fault injection tool (IM-FIT). IM-FIT is an open-source automated software testing tool that is used to evaluate the software robustness of safety-critical systems using mutation-based tests. The proposed ROSMutation library mutates ROS-specific code snippets (publisher, subscriber, params, services, etc.) in the Python code within ROS-compatible software packages using IM-FIT. We evaluated the effectiveness of the ROSMutation library in two scenarios (basic and advanced), applying it to ROS-compatible code through IM-FIT and measuring its ability to assess the software robustness of ROS-compatible and Python-based software packages. The results showed that the ROSMutation library is effective in evaluating software robustness criteria for ROS-compatible and Python based software.

The standardization of the hash-based digital signature scheme SPHINCS+ proceeds faster than initially expected. This development seems to be welcomed by practitioners who appreciate the high confidence in SPHINCS+’s security assumptions and its reliance on well-known hash functions. However, the implementation security of SPHINCS+ leaves many questions unanswered, due to its proneness to fault injection attacks. Previous works have shown, that even imprecise fault injections on the signature generation are sufficient for universal forgery. This led the SPHINCS+ team to promote the usage of hardware countermeasures against such attacks. Since the majority of operations in SPHINCS+ is dedicated to the computation of the Keccak function, we focus on its security. At the core, hardware countermeasures against fault injection attacks are almost exclusively based on redundancy. For hash functions such as Keccak, straightforward instance- or time-redundancy is expensive in terms of chip area or latency. Further, for applications that must withstand powerful fault adversaries, these simple forms of redundancy are not sufficient. To this end, we propose our impeccable Keccak design. It is based on the methodology presented in the original Impeccable Circuits paper by Aghaie et al. from 2018. On the way, we show potential pitfalls when designing impeccable circuits and how the concept of active security can be applied to impeccable circuits. To the best of our knowledge, we are the first to provide proofs of active security for impeccable circuits. Further, we show a novel way to implement non-linear functions without look-up tables. We use our findings to design an impeccable Keccak. Assuming an adversary with the ability to flip single bits, our design detects all attacks with three and less flipped bits. Attacks from adversaries who are able to flip four or more bits are still detected with a high probability. Thus, our design is one of the most resilient designs published so far and the only Keccak design that is provably secure within a bit-flip model. At an area overhead of factor 3.2, our design is competitive with state-of-the-art designs with less resilience.

Recently, a data-driven approach has been widely used at various stages of the system development lifecycle thanks to its ability to extract knowledge from historical data. However, despite its superiority over other conventional approaches, e.g., approaches that are model-based and signal-based, the availability of representative datasets poses a major challenge. Therefore, for various engineering applications, new solutions to generate representative faulty data that reflect the real world operating conditions should be explored. In this study, a novel approach based on a hardware-in-the-loop (HIL) simulation and automated real-time fault injection (FI) method is proposed to generate, analyse and collect data samples in the presence of single and concurrent faults. The generated dataset is employed for the development of machine learning (ML)-assisted test strategies during the system verification and validation phases of the V-cycle development model. The developed framework can generate not only time series data but also a textual data including fault logs in an automated manner. As a case study, a high-fidelity simulation model of a gasoline engine system with a dynamic entire vehicle model is utilised to demonstrate the capabilities and benefits of the proposed framework. The results reveal the applicability of the proposed framework in simulating and capturing the system behaviour in the presence of faults occurring within the system's components. Furthermore, the effectiveness of the proposed framework in analysing system behaviour and acquiring data during the validation phase of real-time systems under realistic operating conditions has been demonstrated. [ABSTRACT FROM AUTHOR]

Copyright of Journal of Engineering & Architectural Faculty of Eskisehir Osmangazi University / Eskişehir Osmangazi Üniversitesi Mühendislik ve Mimarlık Fakültesi Dergisi is the property of Eskisehir Osmangazi University and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)

Traditionally, studies have primarily focused on single event effects in aerospace electronics. However, current research has confirmed that atmospheric neutrons can also induce single event effects in China's advanced technology relay protection devices. Spallation neutron irradiation tests on a Loongson 2K1000 system-on-chip based relay protection device have revealed soft errors, including abnormal sampling, refusal of operation and interlock in the relay protection device. Given the absence of standardized evaluation methods for single event effects on relay protection devices, the following research emphasizes the use of Monte Carlo simulation and software fault injection. Various types of single event upsets, such as single bit upsets, dual bit upsets, and even eight bit upsets, were observed in Monte Carlo simulations where atmospheric neutrons hit the chip from different directions (top and bottom). The simulation results indicated that the single event effect sensitivity of the relay protection device was similar whether the neutron hit from the top or the bottom. Through software fault injection, the study also identified soft errors caused by neutron induced single event upsets on the Loongson 2K1000 system, including failure to execute, system halt, time out, and error result. And the soft error number of system halts and error results exceeded that of time outs and failures to execute in all three tested programs. This research represents a preliminary assessment of single event effects on relay protection devices and is expected to provide valuable insights for evaluating the reliability of advanced technology relay protection devices. [ABSTRACT FROM AUTHOR]

Hardware-in-the-Loop (HiL) testing has emerged as a pivotal technique for validating and enhancing the performance of control systems across various industries, notably in automotive and embedded manufacturing sectors. This paper provides an extensive exploration of HiL testing methodologies and their application in the Internet of Things (IoT) domain. HiL testing involves simulating real-world conditions by integrating specialized simulation software and hardware components, facilitating realistic evaluation of controllers' functionality and behaviour. Different variants of HiL, such as Model-in-the-Loop (MiL), Software-in-the-Loop (SiL), Processor-in-the-Loop (PiL), and Hardware-in-the-Loop (HiL), are discussed within the broader context of XiL (Anything-in-the-Loop) models. The paper underscores the significance of HiL testing in optimizing the development process, reducing costs, and minimizing hazards. It elaborates on the utilization of HiL testing to validate intricate control algorithms, simulate fault scenarios, and assess system behaviour under diverse conditions. The integration of HiL testing with IoT applications is examined, highlighting the potential benefits in areas like smart cities, industrial IoT, healthcare, agriculture, and energy management. The study presents a novel fault injection framework within HiL testing, allowing real-time analysis of complex systems' responses to simulated faults. This framework aids in identifying vulnerabilities and evaluating system reliability, thereby enhancing safety and performance. The authors introduce the concept of sensor schema, Observations & Measurements (O&M), and Sensor Web Enablement (SWE) as key components for efficient sensor data integration, sharing, and interoperability. The paper concludes by emphasizing the indispensable role of Hardware-in-the-Loop testing in fostering innovation, safety, and efficiency in the IoT landscape. By offering a comprehensive overview, analysis, and practical insights into the application of HiL testing methodologies, this research contributes to the advancement of robust and reliable IoT systems. [ABSTRACT FROM AUTHOR]

This paper introduces a new finding regarding single event upsets (SEUs) in configuration memory, and their potential impact on enhancing the performance of deep neural networks (DNNs) on the multiprocessor system on chip (MPSoC) platform. Traditionally, SEUs are considered to have negative effects on electronic systems or designs, but the current study demonstrates that they can also have positive contributions to the DNN on the MPSoC. The assertion that SEUs can have positive contributions to electronic system design was supported by conducting fault injections through dynamic reconfiguration on DNNs implemented on a 16nm FinFET technology Zynq UltraScale+ MPSoC. The results of the current study were highly significant, indicating that an SEU in configuration memory could result in an impressive 8.72% enhancement in DNN recognition on the MPSoC. One possible cause is that SEU in the configuration memory leads to slight changes in weight or bias values, resulting in improved activation levels of neurons and enhanced final recognition accuracy. This discovery offers a flexible and effective solution for boosting DNN performance on the MPSoC platform. [ABSTRACT FROM AUTHOR]

Copyright of Computer Measurement & Control is the property of Magazine Agency of Computer Measurement & Control and its content may not be copied or emailed to multiple sites or posted to a listserv without the copyright holder's express written permission. However, users may print, download, or email articles for individual use. This abstract may be abridged. No warranty is given about the accuracy of the copy. Users should refer to the original published version of the material for the full abstract. (Copyright applies to all Abstracts.)