Search

This paper analyzes an anomalous failure mechanism detected on last generation low voltage power metal oxide semiconductor (MOS) devices at low drain current. Such a behavior, apparently due to a kind of second breakdown phenomenon, has been scarcely considered in literature, as well as in manufacturer data sheets, although extensive experimental tests show that it is a common feature of modern low voltage metal oxide semiconductor held effect transistor (MOSFET) devices. The paper starts by analyzing some failures, systematically observed on low voltage power MOSFET devices, inside the theoretical forward biased safe operating area. Such failures are then related to an unexpected thermal instability of the considered devices. Experimental tests have shown that in the considered devices the temperature coefficient is positive for a very wide drain current range, also including the maximum value. Such a feature causes hot spot phenomena in the devices, as confirmed by microscope inspection of the failed devices. Finally, it is theoretically demonstrated that the thermal instability is a side effect of the progressive die size and process scaling down. As a result, latest power MOSFETs, albeit more efficient and compact, are less robust than older devices at low drain currents, thus requiring specific circuit design techniques.

He atoms were implanted in crystalline and pre-amorphized silicon wafers at doses in the 2×10 16 1×10 17 cm −2 range. Using transmission electron microscopy (TEM) we monitored the evolution of He bubbles into voids upon thermal annealing. Bubbles are formed in both crystalline and amorphous silicon. However, in amorphous material bubble interaction with the moving crystalline–amorphous interface during the epitaxial regrowth prevents their evolution into voids. By implanting He at different target temperatures in crystalline Si, thus by changing the structure of radiation damage, we found that the interaction between point defects and He atoms is essential for the generation of He bubbles and for their subsequent evolution into voids.

Formation and properties of voids in silicon obtained by high dose helium implants are described and discussed in view of their applications in localised lifetime engineering. Voids are stable even after huge thermal budget as observed by transmission electron microscopy analyses. Leakage measurements on p + n diodes as a function of temperature allowed us to determine the hole trap level ( ΔE =0.16 from the Fermi level above the valence band) and the generation and recombination lifetime values. To demonstrate the advantage of the method in power device applications, high-speed IGBTs were fabricated both with voids in the buffer layer or with unlocalised recombination centres. The devices with voids show a lower on-resistance and a fast turn-off behaviour. Map measurements on 150 mm silicon wafers demonstrate the good uniformity that can be reached by the method in an industrial environment.

Boron ions were implanted at 80 keV for a dose of 2 × 1015 cm−2 in crystalline silicon. The silicon crystal was recovered using different annealing processes to produce layers with different secondary defect densities. The quality and the characteristics of the silicon oxide grown on the different surfaces were found to depend on the defects present in the layer immediately under it. The oxide quality was improved by using implanted and annealed silicon with a defect free surface. Iron contaminations, introduced in the wafers at different concentrations (up to 1 × 1015 cm−2), do not affect the oxide layer grown on unimplanted silicon wafers, while it degrades the oxide characteristics of layers grown on implanted and annealed samples. This degradation decreases if the residual damage is reduced by annealing processes.

The diffusion and the electrical behavior of Al implanted in the dose of 1 x 10[sup 13] to 5 x 10[sup 15] cm[sup [minus]2] at 300 keV in capped and uncapped Si is investigated. The Al-based precipitates which are formed when Al concentration exceeds its solid solubility in Si are electrically inactive. The out-diffusion phenomenon that is always present in uncapped samples reduces the Al dose diffused into Si substrate. A study on the electrical activity of Al implanted in Si through SiO[sub 2], Si[sub 3]N[sub 4], and Si[sub 3]N[sub 4]/SiO[sub 2] capping films also is presented. In these capped samples Al segregation in SiO[sub 2] layer occurs. The electrically active doses are small and comparable to that of uncapped samples. The authors studied the diffusivity of Al in bulk SiO[sub 2] and Si[sub 3]N[sub 4] at 1,200 C. The fast Al diffusion through SiO[sub 2] thin layers is driven by a chemical reaction between Al and SiO[sub 2] starting from the SiO[sub 2]/Si interface.

Diffusion mechanisms in crystalline silicon are reviewed emphasizing the role played by the structural defects like vacancies and self-interstitials. These defects control the diffusion process of some transition metals, such as Au and Pt, which undergo fast long-range diffusion as interstitials and become substitutional by replacing a Si atom in a kick-out reaction. The influence of boundary conditions and sample surfaces on the concentration profiles of these metals are analysed in detail. These profiles can be precisely tailored using ion-implantation to achieve a low fluence diffusion source. Fine tuning of the metal profiles is shown to improve greatly the trade-off between dynamic and static characteristics of some silicon power devices like metal-oxide-semiconductor field effect transistors. Moreover, the possibility to obtain a preferential reduction of lifetime by metal doping in a selected area of a semiconductor device is demonstrated.

The electrical behaviour of ion implanted aluminum into silicon was investigated by varying the beam energy in the 80 keV-6 MeV range, the dose in the 1 × 1013–1 × 1014/cm2 range and the annealing procedure. Aluminum atoms precipitate into exten defects at the end of range damage and where the concentration exceeds the solid solubility value (about 2 × 1019/cm3 at 1200°C Escape of Al atoms occurs very easily as soon as they reach the external surface during the thermal diffusion. Using high energy implants, 6 MeV, it was possible to follow in detail the broadening of the diffused profiles. The measured trends between the retained dose and the junction depth and between the outdiffused dose and the annealing time are quite well predicted by the solution of the diffusion equation with the surface acting as a perfect sink for the dopant.

The main purpose of this work has been to carry out a complete analysis by simulation of the behavior of low-voltage power MOSFETs accounting for the effects of the gate parasitic-RC distribution. The use of a gate-mesh low resistance has been analyzed as an overall alternative to more traditional materials. Moreover, a design using mixed materials (poly-silicon material and low resistivity one) has been also investigated. The contribution of the gate metal resistivity has been accounted for through modeling and simulation runs. This study is devoted to the decrease of the switching speed, thus allows obtaining advantageous performances in terms of power losses. Moreover good results are shown that can be achieved in terms of robustness due to a more uniform distribution of the current in switching condition within the device structure. The analysis has been realized by building a complete model of the device useful for behavioral simulations based on a preliminary discretization of the geometry into elementary cells. The achieved results can be exploited to improve the device design especially from the point of view of a continuous scaling process. The increase of the switching speed allows managing both higher powers and operative frequency as it is required by new converters and more demanding applications.

An innovative method to control carrier lifetime locally and efficiently in Insulated Gate Bipolar Transistors (IGBTs) is presented. It is based on the formation of void layers by low-energy and high-dose He implants and annealing. Voids introduce two well-defined midgap trap levels in silicon. HFIELDS simulations demonstrate the increase of surface hole concentration when a well localized recombination region is introduced in the buffer layer. High-speed IGBTs were fabricated both with voids in the buffer layer or with unlocalized recombination centres. Devices with localized bandgap centres show a lower on-resistance with a fast turn-off behavior.

A new, very promising family of IGBTs has been recently carried out in "mesh overlay" technology. If compared with previous generations of IGBTs, new PowerMESH devices show some key improvements such as lower V/sub CE(SAT)/, higher current capability, lower switching times and higher latch up immunity. In this paper a SPICE model for PowerMESH IGBT devices is developed exploiting a new modeling method based on neural networks, in an effort to obtain an optimal trade off among precision, complexity of parameter identification procedures and computational speed. The proposed approach leads to the development of a PSPICE behavioral model of PowerMesh IGBTs including temperature effects both on steady state characteristics and dynamic features. Such a model can be effectively used in standard circuital simulators in order to simulate complex power converters. The proposed approach can be also applied to predict the key features of non existing devices, on the basis of the models of elements of the same family.

A new PSpice model of power MOSFETs has been recently developed aiming to account for the parameter variations with temperature. The present paper discusses the new model in detail and reports static and dynamic validation tests at different working temperatures in the range 25-150/spl deg/C on actual devices. Finally, the model is tested in applications where the power devices are connected in parallel or in series, in order to carry out specific information during critical behavior such as turn-on and turn-off transients.

A new power structure integrating a freewheeling diode in the termination region of a punch-through (PT) insulated gate bipolar transistor (IGBT) is presented. The proposed solution requires virtually no silicon area penalty with respect to a standard IGBT. Static and dynamic experimental results show the correct behavior of both IGBT and freewheeling diode. Further, it is shown that the lateral diode surrounding the multicellular IGBT can support IGBT direct current with low on-state voltage drop. The operation mechanisms of the composite structure and design techniques to improve structure dynamic behavior are investigated through two-dimensional numerical device simulations.

The need of devices for medium-range power converters gives rise to a growing interest for the series connections of IGBTs. In this case the control of the voltage sharing across the string of series-connected devices as well as their protection during the short circuit transients are important issues. In this paper is presented an exhaustive analysis of the electrical quantities and device parameters affecting the voltage sharing across the series strings of IGBTs in short circuit conditions In particular, hard switching fault (HSF) and fault under load (FUL) are investigated, in the case of series connections of devices, by carrying out simulation runs and experimental tests in order to understand the behavior of the IGBTs in these critical conditions. Advantages and disadvantages of the voltage sharing techniques are discussed with reference to the failure in short-circuit occurring on the series connection of devices.

The paper deals with the short circuit behavior during fault under load (FUL) conditions occurring on IGBT devices. The experimental switching transients in FUL with inductive load have been widely investigated. The devices have been tested in several working conditions accounting for the spread of the device characteristics, the parasitic due to the board layout, and the gate driving characteristics aiming to evaluate the switching performances and the influence of the parameters involved into the transient. The effect of the device temperature has been taken into account too. The experimental tests have been carried out using as a workbench a chopper circuit equipped with IGBT devices. As in medium and large power range converters the use of multiple string of IGBT devices is worth to be considered, the parallel and series connections experiencing FUL conditions have been also investigated.

In this paper the behavior analysis of parallel connection of IGBTs under short circuit conditions is presented. The issues of hard switching fault (HSF) and fault under load (FUL) short circuit types are faced by taking into account for the influence of the layout and gate driving parameters. The role of the temperature has been considered too in order to investigate how this quantity affects the IGBTs short circuit phenomenon. An analytical description of the FUL transient is introduced to put in correlation the current and voltage peaks, which are suffered by the IGBT, to the circuit and device parameters. Indeed, the current peak imbalance appearing in a FUL condition is depending on the power layout, on the gate driving conditions and spread on device parameters.

Aluminum-based metallizations are extensively used as electrical interconnections of integrated power microelectronic devices. It is well known that this metal exposed to moisture is highly sensitive to corrosion due to the chemical interaction of aluminum with water. In this paper we report a study of some Al passivation treatments against moisture corrosion, The proposed treatment can be done on the finished wafer without any damage of other device materials and satisfies the die attach and wire-bonding requirements. It consists of a simple chemical dipping into an organic bath containing a phosphating agent. The passivation behavior of the resulting surfaces has been checked by means of pressure cooker test both on the wafer and power metal oxide semiconductor devices assembled in plastic packages. The surfaces resulting in each process step have been analyzed by means of electron spectroscopy for chemical analysis, The passivated surface is formed of one to two monolayers of ortho- and polyphosphate phases directly grafted onto the alumina surface, The same growth process allows fluorine surface contamination reduction.

The sections in this article are 1 Basic BJT Operations 2 Structure and Fabrication Technology 3 Reverse Behavior: Off State 4 Forward Behavior: on State 5 Thermal Ratings 6 Safe Operating Areas 7 Switching Transients 8 Multiple Connections of BJTs 9 Modeling and Simulation 10 Trends in BJT Development

A new PSpice model of power MOSFETs has been developed aiming to account for the parameter variations with the temperature. A new computer aided design package that helps the designer in the parameter extraction procedure is discussed in detail. The model accuracy has been tested by comparison of the simulated waveforms with the experimental traces relative to actual devices.

A new PSpice model of punch-through (PT) IGBTs is developed to account for the presence of the buffer layer and its influence on the dynamic behavior of the device. The recombination and redistribution of charge in the base region of IGBTs during a transient behavior are modeled and represented by equivalent electric circuits. In particular, the effect of the external voltage (clamping voltage) on the tail current decay is modeled. Besides, phenomena such as the "tail bump" and the variation of the slope in the initial part of the output voltage V/sub ce/ during a turn-off transient are modeled. The proposed model is validated by comparing several simulation runs to the experimental traces at different static and dynamic working conditions.

A new PSpice model of power MOSFETs has been developed aiming to account for the parameter variations with the temperature. The paper discusses the new model in detail, showing the close correlation between the new quantities introduced and the experimental evidence that requires an improvement of the simulations carried out by similar available models. Comparison and evaluations of simulation runs (in static and dynamic conditions) obtained by the proposed model and other power MOSFET PSpice models are also presented and discussed. Finally, performances in terms of accuracy, simulation times, advantages and disadvantages of each model in different circuit applications are reported and compared with the experimental traces relative to actual devices.

Localized lifetime control in silicon bipolar devices is presented and discussed. It was achieved by formation of a void layer by He ion implantation. The void formation is reviewed and the void properties are described and carefully considered. Simulations demonstrate the advantages of using localized lifetime control, while the innovative method is applied to fabrication of high speed Insulated Gate Bipolar Transistors.

The purpose of the present paper is to investigate the switching and conduction losses mechanisms in Insulated Gate Devices (IGDs) such as MOSFETs, IGBTs and MCTs in order to give a support to designers of resonant circuits in selecting the more appropriate IGDs to be used on the basis of design requirements.

Double He implants at 40 and 100 keV at several combinations of doses were performed in (100) silicon to form two layers of voids after annealing. Two layers of voids were observed only for thermal treatments lower than 1100/spl deg/C, At higher temperatures a strong interaction between the two void bands is observed inducing their collapse into a single layer.

In this paper a novel SPICE-based simulation tool is presented, suitable to describe the steady-state electro-thermal behavior of new-generation multicellular VDMOS transistors for low-voltage applications. Compared to similar approaches, the proposed one presents substantial improvements: (a) a new electrothermal sub-circuit representation for the elementary transistor is used, which provides an accurate prediction of device characteristics over the temperature range [300 K-400 K] also in quasi-saturation operating mode; (b) the thermal network accounts for both self-heating and thermal interaction effects, is based solely on layout data and is automatically generated; (c) non linear thermal phenomena and layout effects are taken into account.