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Despite a large steric bulk of [C.sub.60], a molecular graphene with a covalently linked [C.sub.60] pendant [hexabenzocoronene (HBC)-[C.sub.60]; 1] self-assembles into a coaxial nanotube whose wall consists of a graphite-like [pi]-stacked HBC array, whereas the nanotube surface is fully covered by a molecular layer of clustering [C.sub.60]. Because of this explicit coaxial configuration, the nanotube exhibits an ambipolar character in the field-effect transistor output [hole mobility ([[mu].sub.h]) = 9.7 x [10.sup.-7] [cm.sup.2] [V.sup.-1] [s.sup.-1]; electron mobility ([[mu].sub.e]) = 1.1 x [10.sup.- 5] [cm.sup.2] [V.sup.-1] [s.sup.-1] and displays a photovoltaic response upon light illumination. Successful coassembly of 1 and an HBC derivative without [C.sub.60] (2) allows for tailoring the p/n heterojunction in the nanotube, so that its ambipolar carrier transport property can be optimized for enhancing the open-circuit voltage in the photovoltaic output. As evaluated by an electrodeless method called flash-photolysis time-resolved microwave conductivity technique, the intratubular hole mobility (2.0 [cm.sup.2] [V.sup.-1] [s.sup.-1]) of a co-assembled nanotube containing 10 mol % of HBC-[C.sub.60] (1) is as large as the intersheet mobility in graphite. The homotropic nanotube of 2 blended with a soluble [C.sub.60] derivative [(6,6)-phenyl [C.sub.61] butyric acid methyl ester] displayed a photovoltaic response with a much different composition dependency, where the largest open-circuit voltage attained was obviously lower than that realized by the coassembly of 1 and 2. ambipolar transport | field-effect transistor | nanotube | photovoltaic | self-assembly doi/10.1073/pnas.0905655106

A full three-dimensional quantum simulation of surface-roughness (SR) in short-channel narrow nanowires based on a 3-D real-space nonequilibrium Green's function (NEGF) approach which allows a complete treatment of mode-mixing mechanism is addressed. The results showed that the SR scattering is mainly responsible for positive threshold-voltage shift in the low-field regime while SR-limited mobility which slowly depends on the linear charge density showed the inefficiency of mode-mixing scattering mechanism for very narrow wires.

Uniaxially strained SOI (SSOI) FinFETs are prepared with high electron mobility and low parasitic resistance and the high electron mobility enhancement on the (110) fin sidewall surfaces is obtained by using effective subband engineering through uniaxial tensile strain along . The high mobility enhancement due to uniaxial strain on the (110) surfaces has resulted from the electron repopulation from the fourfold valleys to the twofold valleys.

Numerical simulations, characterization methods and integration processes are developed to examine and optimize three-dimensional multi-channel field-effect transistor (MCFET) gate stack and series resistance. The impact of a high-[kappa] metal TiN/Hf[O.sub.2] gate stack introduction on the MCFET electrical properties is studied, and the methods to reduce the increase in series resistance by optimizing the source/drain (S/D) shape and the S/D silicide position are discussed.

An optimized multi-channel field-effect transistor (MCFET) structure fabricated on a silicon-on-insulator (SOI) substrate with a silicon-on-nothing (SON) process is presented and its performance is analyzed. The current gain of the MCFET structure, its transport properties and specific electrostatic properties are examined, and it is observed that the bottom channel in narrow devices increases the drain current of the MCFET structure without degrading its electrostatic characteristics.

The requirements for driving gallium nitride (GaN) heterostructure field-effect transistors (HFETs) and the design of a resonant drive circuit for GaN power HFET switches are discussed in this paper. The use of wideband III-nitride (such as GaN) devices today is limited to telecom and low-power applications. The current lack of high-frequency high-power drivers prevents their application in power converters. The proposed circuit is based upon resonant switching transition techniques, by means of an LC tag, to recover part of the power back into the voltage source in order to reduce the power loss. This circuit also uses level shifters to generate the zero and negative gate-source voltages required to turn the GaN HFET on and off, and it is highly tolerant to input-signal timing variances. The circuit reduces the overall power consumed in the driver and thus reduces the power loss. This is particularly important for high-frequency driver operation to take full advantage, in terms of efficiency, of the superior switching speed of GaN devices. In this paper, the topology of the low-power-loss high-speed drive circuit is introduced. Some simulation results and preliminary experimental measurements are discussed. Index Terms--Gallium nitride (GaN) heterostructure field-effect transistors (HFETs), high speed, resonant drive circuit.

Monolithic Active Pixel Sensors (MAPS) using standard low cost CMOS technology available from industrial manufacturers have demonstrated excellent tracking performances for minimum ionizing particles and biomedical imaging applications. The need for highly granular, fast, thin sensor drives an R&D effort, aiming to optimize the intrinsic sensor performances. Following this main issue, we present a design of PhotoFET using CMOS submicron technology in this paper. This structure integrates advantageously an amplification using PMOS transistor inside the sensing element. This provides to the sensing element a high sensitivity to ionizing particles and a large dynamic range. The proposed PhotoFET has been implemented with a standard 0.35 [micro]m CMOS process. In this paper, the PhotoFET architecture is presented and the main measured results are shown. Index Terms--CMOS sensors, correlated double sampling, current mode signal processing.

A new nonlinear charge-conservative scalable dynamic electro-thermal compact model for laterally defused MOS (LDMOS) RF power transistors is described in this paper. The transistor is characterized using pulsed I-V and S-parameter measurements, to ensure isothermal conditions. A new extrinsic network and extrinsic parameter-extraction methodology is developed for high-power RF LDMOS transistor modeling, using manifold deembedding by electromagnetic simulation, and optimization of the extrinsic network parameter values over a broad frequency range. The intrinsic model comprises controlled charge and current sources that have been implemented using artificial neural networks, designed to permit accurate extrapolation of the transistor's performance outside of the measured data domain. A thermal sub-circuit is coupled to the nonlinear model. Large-signal validation of this new model shows a very good agreement with measurements at 2.14 GHz. Index Terms--Field-effect transistor (FET), laterally defused MOS (LDMOS), nonlinear, transistor model.

A scalable approach to the modeling of millimeter-wave field-effect transistors is presented in this paper. This is based on the definition of a lumped extrinsic parasitic network, easily scalable with both the number of fingers and the finger widths. The identification of the extrinsic network parameters is carried out by means of accurate full-wave electromagnetic simulations based on the layout of a single reference device. In the paper, the parasitic effects of the gate/drain manifolds and of the source layout are investigated, leading to the definition of realistic linear scaling rules. The obtained model is experimentally validated by using a family of 0.25[micro]m millimeter-wave GaAs pseudomorphic HEMTs through the accurate prediction of critical performance indicators, such as the linear maximum power gain or the stability factor. Despite the simplicity of the proposed model, it proves to be as accurate as typical scalable models provided by foundries. Straightforward application of the scalable modeling approach to the optimum device geometry selection in a typical design problem is also presented. Index Terms--Electromagnetic (EM) analysis, field-effect transistors (FETs), microwave and millimeter-wave integrated circuits (MMICs), semiconductor device modeling.

The least squares solution for the entire small-signal equivalent circuit is itself a formidable task. In this paper, a systematic approach comprising the total and conventional least squares method in analytically obtaining the small-signal field-effect transistor (FET) parameters values is introduced. The proposed method eliminates the conventional 'cold FET' and 'hot FET' modeling constraints and allows an ease in inline process tracking. Index Terms--Field-effect transistor (FET), small-signal equivalent circuit.

A laterally movable gate field effect transistor (LMGFET) device that directly couples lateral mechanical gate motion to drain current of a FET is presented in this paper. Lateral motion of the FET gate results in a change in channel width, keeping the channel length and the gap between the gate and the oxide layer constant. This results in a change in channel current that, in principle, is linearly proportional to mechanical motion. The operating principle of an LMGFET, along with details of the fabrication process for a depletion-type LMGFET device, is described. Fabricated LMGFET shows an average drain current sensitivity to gate motion of--5.8 [micro]A/ [micro]m at [V.sub.DS] = 20 V and [V.sub.GS] = 0 V for 60-[micro]m gate motion. A model for the fabricated LMGFET is developed based on electrical measurements. The device shows promise both as a sensor and as an actuator in MEMS and other related applications. [2008-0147] Index Terms--Laterally movable gate field effect transistor (LMGFET), MEMS, movable gate.

This study reports a general methodology for making stable high-performance photosensitive field effect transistors (FET) from self-assembled columns of polycyclic aromatic hydrocarbons by using single-walled carbon nanotubes (SWNTs) as point contacts. In particular, the molecules used in this work are liquid crystalline materials of tetra(dodecyloxy)hexabenzocoronenes (HBCs) that are able to self-organize into columnar nanostructures with a diameter similar to that of SWNTs and then form nanoscale columnar transistors. To rule out potential artifacts, 2 different structural approaches were used to construct devices. One approach is to coat thin films of HBCs onto the devices with the SWNT-metal junctions protected by hydrogensilsesquioxane resin (HSQ), and the other is to place a droplet of HBC exactly on the nanogaps of SWNT electrodes. Both types of devices showed typical FET behaviors, indicating that SWNT-molecule-SWNT nanojunctions are responsible for the electrical characteristics of the devices. After thermally annealing the devices, HBC molecules assembled into columnar structures and formed more efficacious transistors with increased current modulation and higher gate efficiency. More interestingly, when the devices were exposed to visible light, photocurrents with an on/off ratio of >3 orders of magnitude were observed. This study demonstrates that stimuli-responsive nanoscale transistors have the potential applications in ultrasensitive devices for environmental sensing and solar energy harvesting. chemistry | field effect transistor | nanofabrication | nanoscience | self-assembly

In this paper, inductive-load switching of a high-voltage lateral JFET (HV-LJFET) on 4H-SiC is investigated with a monolithically integrated driver and with an external driver for high-frequency, high-temperature applications. A new 'capacitor-coupled' gate driver circuitry is proposed and optimized to utilize a standard MOS driver and enable fast switching speed without the need for a negative power supply. Switching times and losses of the silicon carbide (SIC) HV-LJFET are characterized under various driver conditions and device temperatures. The results reveal that the temperature-independent, high switching speed of the SiC LJFET makes it possible to hard-switch at 3 MHz, 200 V, 1.2 A, and 250[degrees]C with good efficiency, significantly higher than silicon devices with similar voltage ratings. Index Terms--High frequency, JFET, power ICs, silicon carbide (SIC).

A study is conducted to evaluate the influence of high-k gate dielectrics in the tunnel field-effect transistor (FET) by comparing it to a standard silicon oxide with same EOT. The results revealed that high-k materials with permittivities more than 30 could be used in CMOS technology and future technological development.

The progress related to synthesis, modeling, and device performance of n-type ZnO nanowire field-effect transistors (FETs) is reviewed. The results from simulations provide insight into the defects such as grain boundaries that lead to a decrease of drain current and dc characteristics of the devices.

An empirical large-signal model for high-power microwave silicon-carbide MESFETs capable of predicting self-heating thermal behavior is presented. A generalized drain-current equation based on pulsed-gate IV characteristics measuring up to 2 A and 58 V is presented along with its dependence on temperature. A thermal subcircuit with a nonlinear thermal resistance characterized by a dc method is used to model the temperature behavior of the device. The effect of substrate trapping is modeled as a gate--source voltage correction. The complete drain-current model accurately predicts pulsed-gate and pulsed-gate-and-drain IV characteristics for various quiescent biases, as well as static IV characteristics. The complete large-signal model is shown to accurately predict S-parameters, large-signal output, and input reflected power across biases and frequencies, and third-order intermodulation products. Index Terms--MESFET, model, nonlinear, self-heating, silicon-carbide (SIC), thermal.

The electric-field induced resistive transition in devices with single layers having perylenetetracarboxylic dianhydride sandwiched between two electrodes is discussed. Due to the migration of metal atoms from metal electrodes to organic thin films the metallic filament can be switched between continuous and discontinuous pathways that give rise to resistive transition in the semiconductor between the metal electrodes.

The article analyses the circuit co-design of indium antimonide (InSb)-based quantum-well field-effect transistors (QWFETs). The InSb-based devices are feasible for ultra fast applications and the QWFETs with sub-100-nm channel length are found to be useful for high-speed applications.

An original empirical approach to deal with nonlinear dynamic thermal effects in electron devices is proposed. The new technology-independent approach is very compact and easy to implement in computer-aided design tools. Therefore, it can be easily coupled with electrical device models in order to obtain accurate electrothermal models that are suitable for nonconstant-envelope RF applications (e.g., pulsed radar). Model equations and identification procedures are derived in this paper. Validation results and comparison with simplified models are also presented both for a simulated field-effect transistor device, as well as for a real heterojunction bipolar transistor device. Index Terms--Behavioral modeling, electrothermal, electrothermal effects, heterojunction bipolar transistors (HBTs), intermodulation distortion, microwave field-effect transistors (FETs), modeling, nonlinear, self-heating, semiconductor device thermal factors, thermal, thermal impedance, Volterra series.