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Elliptic curve scalar multiplication (ECSM) is the primitive operation that is also the main computational hurdle in almost all protocols based on elliptic curve cryptography (ECC). This work proposes a novel ECSM hardware architecture by adopting several optimization strategies at circuit and system levels. On the circuit level, it is based on an efficient finite field multiplier that takes fewer clock cycles, produces low latency, and consumes fewer hardware resources. On the system level, Jacobian coordinates with the Montgomery laddering algorithm and a fast scheduling mechanism to execute group operations are adopted. The proposed ECSM design is synthesized and implemented targeting different FPGAs using Xilinx ISE Design Suite. It takes 1.01 ms on the Virtex-7 FPGA to compute a single ECSM operation, occupies 7.1K slices, and achieves 187 MHz frequency. This provides a 30% improvement in computational time with a significantly lower area-time product with better efficiency. Therefore, the proposed ECSM design is better optimized in terms of speed, area-time product, and throughput per slice and hence is suitable for many ECC applications. [ABSTRACT FROM AUTHOR]

The use of resource-constrained devices is rising nowadays, and these devices mostly operate with sensitive data. Consequently, security is a key issue for these devices. In this paper, we propose a compact ECC (elliptic curve cryptography) architecture for resource-constrained devices based on López–Dahab (LD) projective point arithmetic operations on GF(2m). To achieve an efficient area-power hardware ECC implementation, an efficient digit-serial multiplier is developed. The proposed multiplier is built on a Bivariate Polynomial Basis representation and a modified Radix-n Interleaved Multiplication (mRnIM) method (for area and power complexities reduction). Furthermore, the LD-Montgomery point multiplication algorithm is adjusted for accurate scheduling in the compact ECC architecture to eliminate data reliance and improve signal management. Meanwhile, the area complexity is reduced by reuse of resources, and clock gating and asynchronous counter are exploited to reduce the power consumption. Finally, the proposed compact ECC architecture is implemented over GF(2m) (m = 163, 233, 283, 409, and 571) on Xilinx FPGAs' (Field-Programmable Gate Array) Virtex 5, Virtex 6, and Virtex 7, showing that the efficiency of this design outperforms to date when compared to reported works individually. It utilizes less area and consumes low power. The FPGA results clearly demonstrate that the proposed ECC architecture is appropriate for constraint-resources devices. [ABSTRACT FROM AUTHOR]

Elliptic Curve Cryptography (ECC) based security protocols require much shorter key space which makes ECC the most suitable option for resource-limited devices as compared to the other public key cryptography (PKC) schemes. This paper presents a highly efficient area-delay optimized ECC crypto processor over the general prime field ( $\mathbb {F}_{p}$ ). It is structured on a new novel finite field multiplier (FFM) where several optimization techniques have been incorporated to shorten the latency and hardware resource consumption. The proposed FFM architecture is embedded with a finite field adder/subtractor (FFAS) unit which is utilized to perform FFAS operations instead of deploying a dedicated unit. The Common Z (Co-Z) coordinates with the Montgomery ladder method are used to compute point multiplication, a core operation in all ECC-based crypto protocols. The work also proposes an efficient scheduling strategy to execute low-level finite field arithmetic primitives with minimum latency on the employed finite field arithmetic units. Due to these techniques, the proposed ECC processor is optimized for hardware resources, latency, and throughput. It is captured in Verilog-HDL, synthesized, and implemented on Virtex-7, Kintex-7, and Virtex-6 FPGA platforms using Xilinx Vivado and ISE Design Suite tools. On the Virtex-7 FPGA platform, it computes a single 256-bit scalar multiplication primitive in $0.7~m\text{s}$ , consumes just 6.2K slices, and delivers a throughput of 1428 operations per second. The implementation results show that it is a highly efficient design outperforming the state-of-the-art by providing a better area-delay product and higher efficiency. Therefore, it has the potential to be deployed in many applications where both latency and resource requirements are critical.

Security and privacy issues with Internet of Things (IoT) network make it difficult to use IoT technology. Cryptographic protocols can be put in place on IoT edge nodes to address security flaws. Since the edge nodes have few resources, it is challenging to implement these protocols on them. The key operation in these protocols is finite-field multiplication, and how well it is carried out has a big effect on how well they perform. Therefore, we present in this work a novel irreducible All-One Polynomial (AOP)-based low-complexity bit-serial systolic implementation for multiplication in the binary-extended field. The shown multiplier structure features regular cell architectures and local communication connections between the cells, making it more appropriate for VLSI implementation. When compared to competing multipliers, the complexity analysis of the suggested multiplier reveals a significant savings in area and area-time product. As a result, it is more ideal for cryptographic systems that set additional constraints on area.

The arithmetic of finite fields with characteristic 2 is central in many cryptographic algorithms. Based on the normal basis representation for elements of the finite field F 2 n , quantum circuits for addition and multiplication have complexities O(n) and O (n 3) , respectively. However, the complexity of the quantum circuit performing multiplication in F 2 n can be reduced to O (n 2) provided that F 2 n contains an optimal normal basis. In this paper, a lossless quantum circuit for the affine transforms on F 2 n is designed with the quadratic time complexity for some values of n. Moreover, each constituent of the affine transforms on F 2 n is a unitary operation, and accordingly, the domain of these transforms can be extended to the 2 n -dimensional Hilbert space H ⊗ n . In addition, these transforms are one–one mappings from the set of computational basis states, of H ⊗ n , to itself. This property of affine transforms confirms that these transforms can be used in the encryption algorithms for quantum images because a quantum image uses the computational basis states for storing the color and positional information of pixels. Accordingly, a fast quantum image encryption algorithm combining affine transforms with fractional-order Lorenz-like system is presented for the novel quantum representation of color digital images. A selected pair of affine transforms is used to scramble the position information of the quantum image, while the color information of red, blue, and green layers of the scrambled quantum image is encrypted through controlled right translations determined by the fractional-order Lorenz-like system. Analyses of the time complexity reveal that the proposed quantum image scrambling scheme is exponentially faster than some state-of-the-art schemes. Simulation results confirm that the newly suggested encryption algorithm is fast, robust, and reliable. [ABSTRACT FROM AUTHOR]

We present the first Cortex-M4 implementation of the NISTPQC signature finalist Rainbow. We target the Giant Gecko EFM32GG11B which comes with 512 kB of RAM which can easily accommodate the keys of RainbowI. We present fast constant-time bitsliced F16 multiplication allowing multiplication of 32 field elements in 32 clock cycles. Additionally, we introduce a new way of computing the public map P in the verification procedure allowing vastly faster signature verification. Both the signing and verification procedures of our implementation are by far the fastest among the NISTPQC signature finalists. Signing of rainbowIclassic requires roughly 957 000 clock cycles which is 4× faster than the state of the art Dilithium2 implementation and 45× faster than Falcon-512. Verification needs about 239 000 cycles which is 5× and 2× faster respectively. The cost of signing can be further decreased by 20% when storing the secret key in a bitsliced representation.

Quantum computers represent a serious threat to the safety of modern encryption standards. Within symmetric cryptography, Advanced Encryption Standard (AES) is believed to be quantum resistant if the key sizes are large enough. Arithmetic operations in AES are performed over the binary field F 2 m generated by an irreducible pentanomial of degree m = 8 using polynomial basis (PB) representation. Multiplication over F 2 m is the most complex and important arithmetic operation, so efficient implementations are highly desired. A number of quantum circuits realizing F 2 m multiplication have been proposed, where the number of qubits, the number of quantum gates and the depth of the circuit are mainly considered as optimization objectives. In this work, optimized reversible quantum circuits for F 2 8 multiplication using PB generated by two irreducible pentanomials are presented. The proposed reversible multipliers require the minimum number of qubits and CNOT gates, and the minimum depth among similar F 2 8 multipliers found in the literature. [ABSTRACT FROM AUTHOR]

In 2012, Barbulescu, Detrey, Estibals and Zimmermann proposed a new framework to exhaustively search for optimal formulas for evaluating bilinear maps over finite fields, such as Strassen or Karatsuba formulas. The main contribution of this work is a new criterion to aggressively prune useless branches in the exhaustive search, thus leading to the computation of new optimal formulas. We apply in particular our approach to the short product modulo X 5 and the circulant product modulo (X 5 − 1). Moreover, we are able to prove that there is essentially only one optimal decomposition of the product of 3 × 2 by 2 × 3 matrices up to the action of some group of automorphisms. [ABSTRACT FROM AUTHOR]

In this paper, a high speed elliptic curve cryptographic (ECC) processor for National Institute of Standards and Technology (NIST) recommended prime P − 2 5 6 is proposed. The modular arithmetic components in the proposed ECC processor are highly optimized at both architectural level and circuit level. Redundant-signed-digit (RSD) arithmetic is adopted in the modular arithmetic components to avoid lengthy carry propagation delay. A high speed modular multiplier is designed based on an efficient segmentation and pipelining strategy. The clock cycle count is reduced as result of the segmentation, whereas operating frequency and throughput are significantly increased due to the pipelining. An optimized pipelined architecture for modular division is also presented which is suitable for the design of ECC processor using projective coordinates. The Joye's double and add (DAA) algorithm based on X Y -only common Z (co- Z) coordinate is adopted at the system level for its regular and efficient behavior. The proposed ECC processor is flexible and can be implemented using any field programmable gate array (FPGA) family or standard cell libraries. The proposed ECC processor executes a single elliptic curve (EC) point multiplication (PM) operation in 0.47 ms at a maximum frequency of 327 MHz on Virtex-6 FPGA. The implementation results demonstrate that the proposed ECC processor outperforms the other contemporary designs reported in the literature in terms of speed and area × time metrics. [ABSTRACT FROM AUTHOR]

Abstract The increasing dependency of modern day information transferred over the network demands an increasing need of efficient implementations of security protocols on server and client devices to process the encryption and decryption of messages. This paper presents the design of an efficient scalable and unified Elliptic Curve Cryptography (ECC) coprocessor that takes advantage of the DSP48E slices on Xilinx FPGAs. The proposed coprocessor is able to evaluate the elliptic curve point multiplication (ECPM) for all 15 curves recommended by the National Institute of Standards and Technology (NIST). The DSP48E slices available in Xilinx FPGAs improve the performance of the coprocessor and provide the ability to evaluate dual-field arithmetic. The coprocessor has been implemented on a Xilinx Virtex-5 FPGA and it requires 4244 registers, 8316 LUTs, 2291 slices, 5 BRAMs and 25 DSP48E slices. It can evaluate the ECPM between 0.857 ms and 9.662 ms for prime curves and between 0.239 ms and 4.523 ms for binary curves. This paper also proposes a set of scalable finite field arithmetic blocks that can be programmed to implement different ECPM algorithms. In comparison with other ECC coprocessors in the current literature, the proposed design is very competitive in terms of timing performance and hardware resource utilization, while combining the scalability and dual-field features that are not available in other designs. [ABSTRACT FROM AUTHOR]

In this paper, a high-speed power-efficient VLSI implementation of a finite field multiplier in GF($2^{m}$) is presented. The proposed design has a serial-in parallel-out architecture and performs the multiplication operation using a reordered normal basis. The basic idea is to implement the main building block of the multiplier in domino logic to reduce the critical path delay. Reduction in dynamic power consumption is achieved by limiting the contention current between the keeper transistor and the pull-down network at the beginning of the evaluation phase by employing a new keeper control circuit. The semicustom layout of the multiplier was realized in 65-nm CMOS technology. The post place-and-route simulations showed that the multiplier can perform multiplication correctly up to a clock rate of 3.85 GHz and consumes marginally less power than the static CMOS counterpart (also implemented with custom placement and route). The size of the multiplier is currently recommended by the National Institute of Standards and Technology for binary field multiplication in elliptic curve cryptography. The proposed design methodology can also be used in the implementation of similar finite field multipliers possessing regular architectures. [ABSTRACT FROM AUTHOR]

In this paper we extend a normal basis of a finite field over its base field to a new basis which permits both computationally inexpensive exponentiation and multiplication. We focus primarily on extensions of the finite field F 2 . These bases are motivated by Artin–Schreier theory and we conclude that they are particularly useful in Artin–Schreier extensions; that is, extensions F 2 n of F 2 with n a power of two. [ABSTRACT FROM AUTHOR]

Security and privacy issues with Internet of Things (IoT) network make it difficult to use IoT technology. Cryptographic protocols can be put in place on IoT edge nodes to address security flaws. Since the edge nodes have few resources, it is challenging to implement these protocols on them. The key operation in these protocols is finite-field multiplication, and how well it is carried out has a big effect on how well they perform. Therefore, we present in this work a novel irreducible All-One Polynomial (AOP)-based low-complexity bit-serial systolic implementation for multiplication in the binary-extended field. The shown multiplier structure features regular cell architectures and local communication connections between the cells, making it more appropriate for VLSI implementation. When compared to competing multipliers, the complexity analysis of the suggested multiplier reveals a significant savings in area and area-time product. As a result, it is more ideal for cryptographic systems that set additional constraints on area. [ABSTRACT FROM AUTHOR]

Redundant basis (RB) is one of the appealing representation systems for finite field arithmetic due to its specific features in providing cost-free squaring operation in hardware implementation and because it eliminates the need for modular reduction. In this brief, a new architecture for digit-level finite field multiplication in \mathbb F2^{m} using redundant representation is proposed. Contrary to previously presented redundant basis multipliers, in the proposed architecture one digit of each operand is concurrently fed into the multiplier at each clock cycle which, in turn, reduces the total number of the clock cycles required in the multiplication process. To draw an accurate comparison, the proposed multiplier together with several existing digit-level RB multipliers were fully implemented in 65-nm CMOS technology. [ABSTRACT FROM AUTHOR]

Secure information exchange in resource constrained devices can be accomplished efficiently through elliptic curve cryptography (ECC). Due to the high computational complexity of ECC arithmetic, a high performance dedicated hardware architecture is essential to provide sufficient performance in a computation of elliptic curve scalar multiplication. This paper presents a high performance hardware support for elliptic curve cryptography over a prime field GF ( p ). It exploited a best available possible parallelism of elliptic curve points in projective representation. The proposed hardware for ECC is implemented on Xilinx Virtex-4, Virtex-5 and Virtex-6 FPGAs. A 256-bit scalar multiplication is completed in 2.01 ms, 2.62 ms and 3.91 ms on Virtex-6, Virtex-5 and Virtex-4 FPGA platforms, respectively. The results show that the proposed design is 1.96 times faster with insignificant increase in area consumption as compared to the other reported designs. Therefore, it is a good choice to be used in many ECC based schemes. [ABSTRACT FROM AUTHOR]

Two digit-level finite field multipliers in \mathbb F2^{m} using redundant representation are presented. Embedding \mathbb F2^{m} in cyclotomic field \mathbb F2^{(n)} causes a certain amount of redundancy and consequently performing field multiplication using redundant representation would require more hardware resources. Based on a specific feature of redundant representation in a class of finite fields, two new multiplication algorithms along with their pertaining architectures are proposed to alleviate this problem. Considering area-delay product as a measure of evaluation, it has been shown that both the proposed architectures considerably outperform existing digit-level multipliers using the same basis. It is also shown that for a subset of the fields, the proposed multipliers are of higher performance in terms of area-delay complexities among several recently proposed optimal normal basis multipliers. The main characteristics of the postplace&route application specific integrated circuit implementation of the proposed multipliers for three practical digit sizes are also reported. [ABSTRACT FROM AUTHOR]