124 results on '"Forouzandeh, Behjat"'
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2. Low-power hardware-efficient memory-based DCT processor
3. Novel low-power pipelined DCT processor for real-time IoT applications
4. Image interpolation based on 2D-DWT and HDP-HMM
5. High accurate multipliers using new set of approximate compressors
6. An O(1) time complexity sorting network for small number of inputs with hardware implementation
7. FPGA implementation of an adaptive window size image impulse noise suppression system
8. A comprehensive survey on UHF RFID rectifiers and investigating the effect of device threshold voltage on the rectifier performance
9. Chip Level Statistical Leakage Power Estimation Using Generalized Extreme Value Distribution
10. Image Interpolation Based on 2D-DWT with Novel Regularity-Preserving Algorithm Using RLS Adaptive Filters.
11. A 12.5 Gb/s 6.6 mW receiver with analog equalizer and 1-tap DFE
12. Image Interpolation Based on 2D-DWT with Novel Regularity-Preserving Algorithm Using RLS Adaptive Filters
13. Low Complexity Multiplierless Welch Estimator Based on Memory-Based FFT
14. A 0.5–1 GHz single stage linear-in-decibel VGA with 80 dB gain range in 0.18 μm CMOS
15. A novel ultra low power ASK demodulator for a passive UHF RFID tag compatible with C1 G2 EPC standard protocol
16. High-performance low-leakage regions of nano-scaled CMOS digital gates under variations of threshold voltage and mobility
17. A new method for the analysis of transmission property in carbon nanotubes using Green’s function
18. Chip Level Statistical Leakage Power Estimation Using Generalized Extreme Value Distribution
19. Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits
20. High Performance Image Compression Based on Optimized EZW Using Hidden Markov Chain and Gaussian Mixture Model
21. Accurate Estimation of Joint Probability Density Function of Delay and Leakage for nano-CMOS Circuits
22. Improved Range Analysis in Fixed-Point Polynomial Data-Path
23. FPGA implementation of an adaptive window size image impulse noise suppression system
24. Novel Computation-Efficient Single-Image Super-Resolution Based on Hierarchical Dirichlet Process Using Compound Poisson Process.
25. A Hybrid Time Borrowing Technique to Improve the Performance of Digital Circuits in the Presence of Variations
26. UAFEA: Unified Analytical Framework for IA/AA-Based Error Analysis of Fixed-Point Polynomial Specifications
27. Analysis of stress effects on timing of nano-scaled CMOS digital integrated circuits
28. A Timing Error Mitigation Technique for High Performance Designs
29. Computational Analysis of Transient non-Newtonian Blood Flow in Magnetic Targeting Drug Delivery in Stenosed Carotid Bifurcation Artery
30. Interconnect Challenges and Carbon Nanotube as Interconnect in Nano VLSI Circuits
31. A 0.8-V supply bulk-driven operational transconductance amplifier and Gm-C filter in 0.18 µm CMOS process
32. Estimation of joint probability density function of delay and leakage power with variable skewness
33. 4 Bit Comparator Design Based on Reversible Logic Gates
34. A 0.9 V Supply OTA in 0.18 μm CMOS Technology and Its Application in Realizing a Tunable Low-Pass Gm-C Filter for Wireless Sensor Networks
35. A 12.5Gb/s 6.6mW receiver with analog equalizer and 1-tap DFE
36. Full adder design with GDI cell and independent double gate transistor
37. G4-FET modeling for circuit simulation by adaptive neuro-fuzzy training systems
38. Effects of Device and Peripheral Parameters on Transconductance of Silicon Nanowire Transistors
39. A 12.5Gb/s active-inductor based transmitter for I/O applications
40. A 4mW 3-tap 10 Gb/s decision feedback equalizer
41. A new method for noise analysis in nano-scale VLSI circuits using wavelet
42. Quantum Division Circuit Based on Restoring Division Algorithm
43. Finding optimum value of numerical aperture for the best aerial image quality
44. A new method for the analysis of transmission property in carbon nanotubes using Green’s function
45. Multi-walled carbon nanotube impedance
46. Statistical delay modeling of read operation of SRAMs due to channel length variation
47. A novel ultra low-energy sub-threshold inverter based on nanoscale Field Effect Diode
48. Low-power and high-performance Automatic Gain Control systems based on nanoscale Field Effect Diode and SOI-MOSFET
49. Equivalent Left-Handed/Right-Handed Metamaterial's Circuit Model for the Massless Dirac Fermions With Negative Refraction
50. Effects of device and peripheral parameters on transconductance of silicon nanowire transistors
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