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We present an overview of the performances of FDSOI CMOS transistors down to deep cryogenic temperature, highlighting in particular the benefits brought by the back bias. FDSOI transistors are operational from room temperature down to temperature as low as 100mK. The main DC electrical characteristics, as well as variability properties and reliability are measured and analyzed. We also point out specific behaviors appearing at cryogenic temperature, and discuss their physical origin and modeling.

This paper is dedicated to a review of the international effort to map the future of nanoelectronics from materials to systems for the new electronics industry. The following sections are highlighted: the Roadmap structure with the international teams, the methodology and historical evolution, the various eras of scaling, the new ecosystems and computer industry, the evolving supply chain, the development of SoC and SiP, the advent of the Internet of Everything and the 5G communications, the dramatic increase of data centers, the power challenge, the technology fusion, heterogeneous and system integration, the emerging technologies, devices and computing architectures, and the main challenges for future applications.

International audience; Unreliable mobility values, and particularly greatly overestimated values and severely distorted temperature dependences, have recently hampered the development of the organic transistor field. Given that organic field-effect transistors (OFETs) have been routinely used to evaluate the mobility, precise parameter extraction using the electrical properties of OFETs is thus of primary importance. This review examines the origins of the various mobilities that must be determined for OFET applications, the relevant extraction methods, and the data selection limitations, which help in avoiding conceptual errors during mobility extraction. For increased precision, the review also discusses device fabrication considerations, calibration of both the specific gate-dielectric capacitance and the threshold voltage, the contact effects, and the bias and temperature dependences, which must actually be handled with great care but have mostly been overlooked to date. This paper serves as a systematic overview of the OFET mobility extraction process to ensure high precision and will also aid in improving future research.

session 3: Characterization technqiues and reliability assessment techniques; International audience

International audience; The reliability of mobility evaluation of organic field-effect transistors (OFETs) is a serious issue because numerous overestimated and underestimated mobilities have been reported recently. A reliable approach to accurately evaluate OFET mobility is therefore highly desirable. Here, two commonly employed methods and the Y function method (YFM) were used to extract the mobilities of indacenodithiophene-cobenzothiadiazole (IDT-BT) OFETs with four different contact metals. The mobilities extracted by the commonly used methods varied greatly with the contact metal and channel length, whereas those extracted by the YFM were very stable and approached the intrinsic mobility of IDT-BT. Our results show that the YFM is a precise approach that can be widely used to evaluate OFET mobility.

session T8: Transistor; International audience; For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty as well as the capability to route two additional row-wise signals on individual back-planes. Experimental data are extracted from a 14nm planar Fully-Depleted-Silicon-on-Insulator (FDSOI) 0.078µm 2 SRAM in order to properly model 3D top-tier cells. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/16% read/write access time improvement at VDD=0.8V and a reduction of minimum operating voltage Vmin by 60mV at 6w.r.t. planar SRAMs.

Cet article traite de l’etat de l’art et des perspectives des dispositifs FDSOI (Fully Depleted Silicon On Insulator). Les avantages de ces technologies pour les applications «More Moore» sont rappeles, avant d’exposer leurs proprietes electriques, ainsi que les principales solutions pour leur amelioration. L’evolution de ces technologies vers de nouvelles architectures multigrilles et 3D, qui sont non seulement completement desertees mais aussi totalement inversees, pour les composants les plus integres est ensuite mise en exergue. Les technologies emergentes, basees sur d’autres types de transport des porteurs, des materiaux innovants et des structures hybrides sont egalement detaillees.

International audience; Future ICs are facing dramatic challenges in performance as well as static and dynamic power consumption, which could be overcome using disruptive concepts, device architectures, technologies and materials. Promising solutions includes III-V channels, heterojunctions, 2D layers, multi-gates structures, nanowires (NWs), tunnel FETs (TFETs), ferroelectric FETs (Fe-FETs), and hybrid devices. In the domain of small slope switches, which are very interesting for ultra low power operation, TFETs, Fe-FETs and hybrid devices seem very promising. Thus far, no one has experimentally demonstrated a TFET that has simultaneously both a CMOS-competitive driving current Ion and a sub-60 mV/decade subthreshold swing over several decades. But recently, substantial improvements of TFET and hybrid device performance have been reported, showing that these novel device architectures using new materials and carrier transport could be used for several applications.

International audience; Conjugated polymers came to an unprecedented epoch that the charge transport is limited only by small disorder within aggregated domains. Accurate evaluation of transport performance is thus vital to optimizing further molecule design. Yet, the routine method by means of the conventional field-effect transistors may not satisfy such a requirement. Here, it is shown that the extrinsic effects of Schottky barrier, access transport through semiconductor bulk, and concurrent ambipolar conduction seriously influence transport analysis. The planar transistors incorporating ohmic contacts free of access and ambipolar conduction afford an ideal access to charge transport. It is found, however, that only the planar transistors operating in low-field regime are reliable to explore the inherent transport properties due to the energetic disorder lowering by the lateral field induced by high drain voltage. This work opens up a robust approach to comprehend the delicate charge transport in conjugated polymers so as to develop high-performance semiconducting polymers for promising plastic electronics.

Best paper award; session 9: Novel Materials and Technologies; International audience; Recent developments in CMOS devices such as FinFET, FDSOI or stacked nanowire FETs (SNWFETs) have led the industry to consider increasingly complex integration processes while aiming at smaller and smaller devices. This paper proposes new concepts of device integration based on the use of hydrogen silsesquioxane (HSQ). Recently employed to replace polysilicon sacrificial gate in gate last processes, its use could also be extended for building the whole transistor level including device lateral insulation, multi-workfonction layouts, self-aligned contacts and possibly the first layer of metal interconnects. If several EUV masks could be employed for such a use, HSQ patterning once enhanced by multi-electron beam lithography, could allow to perform all these features within a single exposure step without involving any conventional etching or stripping steps.

International audience

session 8: advanced CMOS and New Devices Concepts; International audience; Stacked Nanowires FETs are proposed to replace FinFET and FDSOI for sub-7nm nodes. While most studies demonstrate the performances gain offered by such structures, mechanical stability of the suspended silicon channels needs to be considered. This paper provides a fully mechanical analytical description of nanowire stacks to explain the occurrence of buckling phenomena of silicon channels.

Due to the unavoidable short channel effects associated with planar bulk silicon MOSFET scaling, FinFET and FDSOI have become the most used solutions for the latest generations of CMOS. Gate control over the channel is excellent and performances are enhanced due to the increased effective width in the case of FinFET [1], and due to the forward body biasing solution in the case of FDSOI. However, after several generations of industrially produced FinFET and FDSOI, one crucial question will arise: how far can those technologies be scaled down? Currently, nanowire (NW) transistors have been proven to be excellent candidates for advanced technology nodes. Specifically, electrostatic control is improved over FinFET for better performance and energy savings. Over the last ten years, many developments on nanowire fabrication and nanowire FETs have been proposed [2] [3] [4] [5]. Today, stacking several nanowires at such scale paves the way for a significant increase in the effective width and current density along with substantial savings in device footprint. Stacked nanowires can be implemented with different geometries such as circular or square cross-sections. However, we recently confirmed [5] among other studies [6] that thin and wide devices, also labelled as nanosheets, provide the best performances with respect to the FinFET technology. A further attractive aspect for the use of nanowires in transistors, is that it may be possible to keep some of the flexibility from the planar technologies. In contrast, FinFET technology imposes a discrete partitioning of the active area. In order to increase the output current of a given FinFET based gate, it may be necessary to add another fin to increase the footprint by one fin pitch. Using nanosheets transistors, channel width can be tuned to obtain the required amount of current with limited impact on footprint as discussed in [7]. Stacked nanowire technology is also appealing as one possible solution due to the fact that their integration can be derived from FinFET. Several groups are currently working on their integration trying to minimize the variations from FinFET Gate-Last process [8]. Two options were identified and labelled as NW first and NW last referring to the fabrication of the NW stack. In the former, several successive epitaxies are performed and patterned to form the active zone as a vertical fin, after which silicon or silicon germanium needs to be removed in order to leave suspended silicon or silicon germanium channels. In the NW last integration, selective removal of silicon germanium happens in between the spacers after the removal of the sacrificial gate. In this case, an etch stop layer must be created to prevent the final gate penetrating under the spacers. This etch stop layer must also be low K in order to recreate the missing spacer material in between the NWs. Due to this requirement, an alternative integration has also been investigated. In the NW first option the selective removal of silicon germanium is done before the first spacer patterning and deposition. This method is also coupled with the use of a hydrogen silsesquioxane (HSQ) resist. This flowable oxide can be exposed through the silicon nanowires and the remaining material left after developing can be used as a sacrificial gate during the gate last process. The spacer deposited afterward is able to wrap around the NWs and the oxide temporary gate. As a consequence, this method provides self-aligned gate and spacer. In recent years, we have also come to focus on carrier transport in NW devices. We have produced several NW-FETs in trigate and Ω-gate shapes on SOI in which we measured electron and hole mobility. Face related transport was observed and improved by using proper strain engineering. Strained SOI and silicon germanium raised source and drain were found to have a significant impact on mobility [4]. Currently, this work is also being integrated in order to boost the performances of our stacked NW-FETs. In this paper we propose a review of the NW architecture and of different integration concepts. Several key points for the performance optimization will be pointed out. [1] Natarajan, S. et al. IEDM, 2014 [2] Ernst, T. et al. IEDM 2006 [3] Coquand, R. et al. VLSI 2013 [4] Barraud, S. et al. VLSI 2013 [5] Gaben, L. et al. SSDM 2015. [6] Kim, Seong-Dong et al. S3S 2015 [7] Lacord, J. et al. SSDM 2012. [8] Lauer, I. et al. VLSI 2015

Gate-to-channel capacitance Cgc(Vg) data obtained on FD-SOI MOS devices with gate lengths down to 35 nm are first reported. Thus, a 2D numerical simulation procedure allowing to calculate the total device capacitance and parasitic capacitances is developed. This enabled us to discriminate the respective contributions of all parasitic components such as spacer, overlap, inner fringe and buried oxide capacitances in the structure.

Low-frequency noise (LFN) in double-gate (DG) In–Ga–Zn–O (IGZO) thin-film transistors (TFTs) is studied to investigate the origin of performance improvement. We found that thinning down the IGZO film enhances such improvements. With 7-nm IGZO, the mobility is raised by a factor of 3.77, and the subthreshold slope is reduced to 0.17 V/decade from single-gate to DG mode. Device simulations show that bulk transport inside IGZO film emerges as the two gates field effects get coupled. The LFN results reveal a transport transition from surface to bulk and disclose the superior bulk transport that experiences slight phonon scattering with a small Hooge parameter $\alpha _{H }= 4.44 \times 10^{\mathrm {-3}}$ , whereas the surface transport undergoes serious charge trapping with surface trap densities about $2 \times 10^{11}$ eV $^{-1}$ cm $^{-2}$ .

A development of the conventional transfer-length method (TLM) for organic transistors’ contact resistance evaluation is proposed. By adding the dissipated power in access resistance and in the channel, we found that TLM can be extended to the non-linear region, i.e., up to saturation regime, which is widely believed to be a barrier for TLM application now. To improve the extraction accuracy and stability, a modified TLM version is used for the operation at small gate voltages. This modified power TLM is applied to polymer and pentacene field-effect transistors and proved as a useful tool for the contact resistance evaluation as a function of gate and drain voltages from common current–voltage characterizations.

Close correlation between low-frequency noise and charge transport in pentacene transistors is observed. The trap density evolving with pentacene deposition reveals transformation of growth phase and different transport mechanisms. It explains the greatly altered mobility and contact resistance in which the upper surface's trapping plays an important role. Inspecting contact noise shows high density of traps at contacts that result possibly from pyramid like growth of pentacene or contact damage or both.

SOI partially depleted body-contact MOSFETs were subjected to static and dynamic hot carrier stress. Drain current was investigated by means of Deep Level Transient Spectroscopy and switch-ON transient analysis in a wide temperature range. Under static degradation regime, drain current behaviour was determined by the creation of two discrete traps most likely located in the drain vicinity; a hole trap cited in the literature and a defect of metastable nature. Under dynamic degradation regime, drain current behaviour was determined by body–Si/SiO 2 interface-state generation. Experimental data and fitting results based on stretched exponential law are in accordance.

Silicon On Insulator (SOI)-based devices seem to be the best candidates for the ultimate integration of ICs on silicon. The performance and physical mechanisms are addressed in single- and multi-gate thin film Si, Ge and III-V MOSFETs. The impact of tensile or compressive uniaxial and biaxial strains in the channel, of high k materials and metal gates as well as metallic Schottky source-drain architectures are discussed. The interest of SOI-based emerging and beyond-CMOS nanodevices for long term applications, based on nanowires, carbon electronics or small slope switch structures is presented. Finally, the possible 3D integration of multi-channels and stacked nanowires is also shown.

International audience; The historic trend in micro/nano-electronics these last 40 years has been to increase both speed and density by scaling down the electronic devices, together with reduced energy dissipation per binary transition. We are facing today dramatic challenges dealing with the limits of energy consumption and heat removal, inducing fundamental tradeoffs for the future ICs. A substantial reduction of the static and dynamic power is strongly needed for the development of future high-performance/ultralow-power terascale integration and autonomous nanosystems.This chapter of the tutorial book addresses the main trends, challenges, limits, and possible solutions for strongly reducing the energy per binary switching. Several paths are possible, the most promising one being the reduction of static and dynamic energy consumption using conventional logic with a reduction in the stored energy and therefore a decrease of device capacitance C (device integration) and applied bias V, together with a decrease of leakage currents of nanodevices.The best potential solutions are ultrathin-film SOI (silicon-on-insulator) and multi-gate devices, nanowires, and small-slope switches (tunnel FETs, ferroelectric gate FETs, NEMS) using alternative channel, source/drain, and gate materials. We will present the main challenges to continue More’s law, the novel materials and device architectures, and the possible combination of these boosters, needed for the development of future ultralow-power ICs.

The historic trend in micro/nano-electronics these last 40 years has been to increase both speed and density by scaling down the electronic devices, together with reduced energy dissipation per binary transition, and to develop many novel functionalities for future electronic systems. We are facing today dramatic challenges for More Moore and More than more applications: substantial increase of energy consumption and heating which can jeopardize future IC integration and performance, reduced performance due to limitation in traditional high conductivity metal/low k dielectric interconnects, limit of optical lithography, heterogeneous integration of new functionalities for futures nanosystems, etc. [1-16]. Therefore many breakthroughs, disruptive technologies, novel materials, and innovative devices are needed in the next two decades. With respect to the substantial reduction of the static and dynamic power of future high performance/ultra low power terascale integration and autonomous nanosystems, new materials and novel device architectures are mandatory for ultimate CMOS and beyond-CMOS eras, as well as new circuit design techniques, architectures and embedded softwares. Alternative memories, especially PCRAM, RRAM or MRAM will be useful for pushing the limit of integration and performance beyond to those afforded by present Non-Volatile, DRAM and SRAM memories. In the interconnect area, optical and RF interconnects, carbon or other 2D materials can overcome the present limitations of copper interconnects. Concerning ultimate processing technologies, EUV lithography, immersion multiple patterning, multi ebeam maskless or imprint lithography, as well as self-assembly of nanodevices could be used for different applications. Future autonomous nanosystems will also need the development of nanoscale high performance novel functionalities, which could be integrated on CMOS platforms. In this respect, nanostructures and nanodevices, especially nanowires, are of great interest for instance for improving the sensitivity, resolution, selectivity, energy consumption and response time of nanosensors, and for solar, mechanical and thermal energy harvesting. Parallel or sequential processes could be used for the integration of these future high performance sustainable, secure, ubiquitous and pervasive systems, which will be of high added value for many applications in the field of detection and communication of health problems, environment quality and security, secure transport, building and industrial monitoring, entertainment, education, etc. The talk will focus on the main trends, challenges, limits and possible solutions for future high performance and ultralow power nanoscale devices in the CMOS and Beyond CMOS arena, including ultra-thin films, multi-gates, nanowires and small slope switches. References 1. F. Balestra, Nanoscale CMOS: Innovative Materials, Modeling and Characterization, Francis Balestra Ed., ISTE-Wiley, 2010 2. F. Balestra, Beyond CMOS Nanodevices (Vol. 1 and 2), Francis Balestra Ed., ISTE-Wiley, 2014 3. F. Balestra et al, IEEE Electron Device Letters EDL-8, p. 410, 1987 4. C. Hu et al, VLSI 2008, p. 14 5. M. Luisier et al, IEEE EDL 30, p. 602, 2009 6. F. Conzatti et al, IEDM 2011, p. 95 7. G. Dewey et al, IEDM 2011, p. 785 8. J. Appenzeller et al, Phys. Rev. Lett. 93, 196805, 2004 9. F. Padilla et al, IEDM 2008, p. 171 10. K. Boucart et al, ESSDERC 2009, p. 452 11. F. Mayer et al, IEDM 2008, p. 16 12. D. Esseni et al, IEEE TED 60, p. 2802, 2013 13. S. Brocard et al, IEDM 2013, p. 5.4.1 14. M.H. Lee, IEDM 2013, p. 104 15. S. Brocard et al, IEEE-EDL 2, p. 184, 2014 16. M. Pala et al, J. Elec. Dev. Soc., 2014. Acknowledgements: The author would like to thank the Sinano Institute Members and Partners of Nanosil and Nanofunction FP7 European Networks of Excellence.