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For the purpose of enhancing the performance of interior permanent magnet synchronous motors (IPMSMs) sensorless control, a flux observer based on a third‐order generalized integrator with enhanced frequency‐locked loop (TOGI‐EFLL) is introduced in this paper. Compared with the traditional second‐order generalized integrator with frequency‐locked loop (SOGI‐FLL), the proposed TOGI‐EFLL can effectively mitigate the direct current (DC) bias stemming from non‐ideal factors, such as the inverter non‐linearities and detection errors, without introducing additional parameters. Initially, the active flux observer model and the limitations of the conventional SOGI‐FLL are presented. Subsequently, the proposed flux observer based on TOGI‐EFLL has been intensively investigated. Furthermore, the design of the damping factor and the digital implementation of the algorithm are developed to ensure seamless integration into digital systems. Finally, the effectiveness of the proposed sensorless control strategy is validated through the comprehensive experimental results. [ABSTRACT FROM AUTHOR]

Abstract For the purpose of enhancing the performance of interior permanent magnet synchronous motors (IPMSMs) sensorless control, a flux observer based on a third‐order generalized integrator with enhanced frequency‐locked loop (TOGI‐EFLL) is introduced in this paper. Compared with the traditional second‐order generalized integrator with frequency‐locked loop (SOGI‐FLL), the proposed TOGI‐EFLL can effectively mitigate the direct current (DC) bias stemming from non‐ideal factors, such as the inverter non‐linearities and detection errors, without introducing additional parameters. Initially, the active flux observer model and the limitations of the conventional SOGI‐FLL are presented. Subsequently, the proposed flux observer based on TOGI‐EFLL has been intensively investigated. Furthermore, the design of the damping factor and the digital implementation of the algorithm are developed to ensure seamless integration into digital systems. Finally, the effectiveness of the proposed sensorless control strategy is validated through the comprehensive experimental results.

Although facial landmark localization (FLL) approaches are becoming increasingly accurate in identifying facial components, one question remains unanswered: what is the impact of these approaches on subsequent, related tasks? In this paper, we focus on facial expression recognition (FER), where facial landmarks are used for face registration, which is a common usage. Since the common datasets for facial landmark localization do not allow for a proper measurement of performance according to the different difficulties (e.g., pose, expression, illumination, occlusion, motion blur), we also quantify the performance of recent approaches in the presence of head pose variations and facial expressions. Finally, we conduct a study of the impact of these approaches on FER. We show that the landmark accuracy achieved so far by optimizing the euclidean distance does not necessarily guarantee a gain in performance for FER. To deal with this issue, we propose a new evaluation metric for FLL that is more relevant to FER. [ABSTRACT FROM AUTHOR]

Abstract A novel frequency‐to‐voltage converter based phase‐locked loop (PLL) is proposed to overcome the inability of a frequency‐to‐voltage converter based frequency‐locked loop to lock phase. The proposed dual‐loop PLL adds variable phase‐locking capability, such that the phase locking angle can vary from 0–360°. The additional variable phase‐locking can be applied in data communication in the form of phase modulation. The design is targeted for a 0.5‐μm CMOS process. The proposed design generates a 480 MHz clock from a reference clock of 15 MHz. In simulation, the proposed PLL locks within 3.56 μs while consuming 1.61 mW of power.

This work presents an improved cascaded second-order generalized integrator (I-CSOGI) controlled photovoltaic system (PVS), which functions as an islanded system during grid interruption without energy storage. Here, a single-stage PVS structure is used, simplifying the control by automatically regulating the PV array operating point and dc-link voltage during the grid outage. The I-CDSOGI algorithm is exercised to determine the sensed voltages angle, frequency, and harmonics free positive sequence components of the sensed voltages and load currents. The advantage of the presented I-CDSOGI over the existing CDSOGI algorithm is that the gain of its frequency-locked loop is changed adaptively. It reduces the spurious change in the frequency during the sudden phase jump, which is experienced by the load voltages during synchronization. Hence, the repeated tripping of the power electronics switches, which isolates the PVS from the local grid, is reduced, and smooth synchronization is achieved. Furthermore, the cascading of two second order generalized integrator (SOGI) blocks eliminates the dc offset from the sensed signals and boosts the overall harmonics rejection capability, which enhances the angle and frequency estimation performance. A comparison is made to showcase the benefits of I-CSOGI compared with the existing SOGI-based methods in the PVS. [ABSTRACT FROM AUTHOR]

The control of a microgrid is quite challenging thus this work implements a robust and fast control technique based on an enhanced second-order generalized integrator with a modified frequency locked loop (ESOGI-MFLL) for switching operation between an islanded and the grid-connected mode. For phase angle estimation, a circular limited cycle oscillator frequency locked loop with an inner loop filter (CLO-FLL-WIF) is implemented instead of a conventional phase-locked loop technique to provide better synchronization performance for polluted grid voltages. This microgrid is combing a solar photovoltaic (PV) generation, a synchronous reluctance generator for pico-hydro generation, and the battery, which works in both standalone and grid-connected modes while feeding local loads uninterruptedly. The output power conversion of a PV array is influenced by irradiation of the solar PV array; therefore, a maximum power point tracking namely an incremental conductance method is used. The implemented control techniques are used for fundamental extraction of load components of voltage and currents for assessment of reference currents with their respective phases of synchronization while maintaining the required IEEE power quality standard-519. In addition, the comparative results validate the faster response of ESOGI-MFLL control algorithm to the existing control algorithm. Simulated and test results of a microgrid for islanded, switching mode, and grid-connected mode demonstrate its performance under load unbalance and generation perturbation. [ABSTRACT FROM AUTHOR]

This letter demonstrates that the second-order generalized integrator-based frequency-locked loop (SOGI-FLL) with a soft startup/rate limiter essentially incorporates an adaptive feedforward relying on a priori information of transient input. When a fair parameter is tuned, the soft startup and the limiter give a similar performance. The shortcoming is that they have a deceleration blind zone, depending on the frequency constraints and SOGIs gain. If the allowed rate of change of frequency (RoCoF) is fixed, the fast response FLL can weaken this shortcoming. Specifically, if the RoCoF of low-inertia grids is considered, they could produce a severely biased estimation under the harmonics and dc offsets. The experimental results are given to validate the claims. [ABSTRACT FROM AUTHOR]

In this article, a new microwave frequency-locked-loop (FLL)-based sensor is proposed for complex permittivity measurement of liquid solutions. An interdigitated electrode split-ring resonator (IDESRR) is embedded in the FLL and used as a sensing device to distribute electric field in the near-field region and sense the permittivities of the liquid solutions with different concentrations. When the test liquid is placed on the IDESRR, a deviation will be introduced to the resonance frequency based on the perturbation theory. This frequency deviation accompanies a corresponding phase shift in the FLL operating frequency. The phase-shifted signal then leads the FLL to output a frequency-modulated (FM) signal, whose frequency deviation depends on the concentration level of the test liquid. The quadrature frequency discriminator is used to demodulate this FM signal and transfer it into dc voltages, $V_{I}$ and $V_{Q}$. Reference liquids with known permittivities are used to calibrate the proposed sensor and relate the measured voltages to the dielectric constant and loss tangent. In this article, the water–ethanol mixtures and water–glucose solutions are used as the test liquids to evaluate the measurement performance of the proposed FLL-based permittivity sensor. The measured results obtained using the proposed sensor agree very well with those obtained using the commercial dielectric probe. Moreover, since the proposed permittivity sensor has the benefits of a simple system architecture, high sensitivity, and not requiring a vector network analyzer (VNA), it has great potential to be developed as a new type of biomedical sample sensor. [ABSTRACT FROM AUTHOR]

This article proposes a cascaded integral action-based filter by relying on the orthogonal output of a $T/4$ delay block. The proposed filter employs an integrator together with mechanisms involving feedback of the filtered signal and feedforward of its orthogonal input. Based on this approach, the proposed filter addresses the problem of initial state when applying a direct integral action to a sinusoidal voltage. More so, the proposed filter provides notch filtering characteristics at certain harmonic frequencies, thereby achieving improved harmonic rejection in comparison to existing second-order generalized integrator filter. Without frequency adaptivity, the proposed filter achieves fast response, and more importantly, provides excellent filtering of harmonic components at off-nominal frequencies of the supply voltage. Furthermore, dc-offset rejection in the proposed filter is considered together with its FLL implementation for frequency, phase angle, and amplitude estimations. Linearized model and stability evaluation of the proposed filter’s FLL are presented while detailed analytical, simulation, and experimental validation of the proposed filter’s performance for applications involving voltage parameter estimation for synchronization purposes and reference signal generation are provided. Results obtained demonstrate superiority of the proposed filter in terms of harmonic rejection and estimation speed when compared to existing filtering techniques. [ABSTRACT FROM AUTHOR]

This article proposes an enhanced frequency-locked loop method for the single-phase grid frequency estimation under dc offset and both odd and even harmonics conditions. The proposed method relies on an adaptive recursive discrete Fourier transform-based frequency error detector and an integral controller. It offers a relatively simple structure and computationally efficient method. It can provide accurate frequency estimation at steady state under grid disturbances and takes a dynamic time of around one and half cycles of the fundamental frequency. The improved performance of the proposed method is verified by comparing it with the results of several existing methods reported in the technical literature. The efficacy of the proposed method is proved using simulated and real-time experimental results. [ABSTRACT FROM AUTHOR]

Generalized integrator-based orthogonal signal generator phase-locked loops (GI-OSG PLLs) are very popular in single-phase grid synchronization. Generally speaking, the OSG of this PLL is realized from a second-order integrator perspective. As a result, the OSG implementation impacts the PLL dynamics. Improving the PLL performance by employing a reduced-order OSG implementation is the main motivation for this paper. Therefore, a reduced order-OSG PLL is proposed. In the proposed PLL, a single state and two output equations are employed to obtain a pair of orthogonal signals. This results in the loss of orthogonality between the OSG outputs and the single-phase supply voltage. Also, harmonic filtering capability provided by SOGI-OSG becomes non-existent. These issues are resolved by incorporating steady-state phase angle-offset error compensation at the PLL output and a moving average filter (MAF) within the PLL loop. To counteract the influence of MAF on the PLL’s stability and dynamics performance, a phase-lead compensator is designed. Through experimental studies, it is shown that the proposed reduced order-OSG PLL offers excellent dynamic performance. Also, the proposed PLL achieves minimal fluctuation of PV power when employed for grid synchronization of a PV system. [ABSTRACT FROM AUTHOR]

The multiple second-order generalized integrator (MSOGI), which is composed of parallel second-order generalized integrators (SOGI), is widely used in grid synchronization and signal extraction, and it usually suffers from dc offset issue. In continuous domain, low-pass filter (LPF) can be added to SOGI to eliminate the dc offset in its quadrature channel. However, in digital implementation, directly discretized LPF-based methods may not be able to eliminate dc offset and ac discretization error simultaneously, where the steady-state error will also be introduced by the conventional frequency-locked loop (FLL). In this article, a modified impulse invariant method is adopted to discretize SOGIs, which presents zero ac errors and good dynamics, but shows dc offset in both output channels. Then, an LPF is introduced to eliminate the dc offset of the discrete SOGI, forming a discrete SOGI-LPF. And, a discrete MSOGI-LPF (DMSOGI-LPF) is formed by paralleling multiple DSOGI-LPFs, which can extract different frequency components. Furthermore, a discrete FLL is proposed to estimate the frequency of the input signal, which suppresses the influence of the dc offset and achieves good dynamics. Finally, the stability analysis of the proposed method based on discrete linear-time periodic (LTP) model is provided. The effectiveness of the proposed method and its discrete LTP model are validated through experimental results. [ABSTRACT FROM AUTHOR]

An accurate and prompt estimation of phase angles, frequency, and magnitudes of the grid voltage is extremely important in paving a good platform for a fast and reliable operation of power grid monitoring, protection, and control. The phase-locked loop (PLL) served this purpose for decades, while the concept of the frequency-locked loop (FLL) has been proposed more recently. Even though the FLL and the PLL share some similarities, some differences still exist. Further research on FLLs can boost their capabilities and open up new windows in designing devices for grid synchronization. Multiple delayed signal cancellation (MDSC) filters are a peculiar system of filters. Their applications to FLLs can enrich FLL’s performance. This article focuses on applying the stationary reference frame MDSC filters at in-loop and prefiltering stages of the FLL and compares its effectiveness with widely used cascaded delayed signal cancellation (CDSC) and complex bandpass filter (CBF) based filtering techniques. The application of the $K$ -factor-methodology-based controller design to FLLs has also been explored for dynamic performance enhancements. A new cascaded multiple delayed signal cancellation (CMDSC) filter is proposed and is compared with its CDSC counterpart proposed in the literature to address the effects of dc offsets and imbalances under adverse grid conditions. The effectiveness of the proposed method is verified through OPAL-RT real-time simulations and dSPACE ds1104 and TMS320F28335 microcontroller experimental test bench. [ABSTRACT FROM AUTHOR]

A fully integrated 490-GHz receiver (RX) adopting a dual-locking receiver-based FLL (DL-RBFLL) is presented. The proposed RBFLL structure saves the power consumption by reusing the existing blocks in RX instead of the power-hungry blocks such as dividers and buffers operating at sub-THz. Contrary to the single-loop implementation, the dual-loop RBFLL, which consists of the coarse and fine locking loops, extends the locking range by six times with negligible additional power dissipation. In the RF front-end (FE), the proposed 2nd-order sub-harmonic mixer (SHM) enhances interport isolation and suppresses the undesired LO leakage using a simple passive network. In the IF path, a 2-stage low-noise amplifier (LNA) followed by a 10-stage programmable gain amplifier provides a controllable gain of 0–80 dB with 4-dB step. An N-path filter, which serves as a high-Q bandpass noise filter, improves SNR in the IF path and thus RX sensitivity. Implemented in a 65-nm CMOS, the 490-GHz RX achieves the measured noise figure of 51.1 dB and noise equivalent power (NEP) of 0.85 pW/Hz $^{0.5}$ for the noise bandwidth of 17 MHz. The estimated sensitivity of the proposed RX is −92.9 dBm for a 1 kHz noise bandwidth, which dissipates 31.8 mW from a 1.2-V supply. [ABSTRACT FROM AUTHOR]

This paper presents a novel phase-tracking robust-synchronization-loop (RSL) to track the phase and frequency of the grid voltage. A detailed analytical model of the proposed RSL algorithm is presented. Further, a state-space small-signal model is developed, including the dynamics of a grid-connected converter and its controller. From the small-signal analysis, it is shown that the eigenvalues associated with the states of the RSL remain in the left half-plane even for a very weak grid condition with a grid impedance of 1.0 pu, thus, it provides better stability property with the grid-connected converters. In order to show the effectiveness of the proposed RSL, simulation results are provided for different scenarios of the grid conditions such as voltage and frequency disturbance, unbalance grid condition and grid faults. Further, the performance of the RSL algorithm is tested by experiment in lab. The results show that the proposed method effectively tracks the phase and frequency of the grid voltage and maintains the good synchronism of the converters during different disturbances. [ABSTRACT FROM AUTHOR]

This article presents a 16-MHz RC frequency reference implemented in a standard 180-nm CMOS process. It consists of a frequency-locked loop (FLL) in which the output frequency of a digitally controlled oscillator (DCO) is locked to the frequency-phase characteristic of a Wien bridge RC filter. Since it is made from on-chip resistors and capacitors, the filter’s characteristic is temperature dependent. To compensate for this, the control signal of the DCO is derived by digitizing the filter’s output phase and combining it with the digital output of a Wheatstone bridge temperature sensor. After a two-point trim, this digital temperature compensation scheme achieves an inaccuracy of ±90 ppm from −45 °C to 85 °C. The frequency reference draws 220 $\mu \text{A}$ from a 1.8-V supply, with a supply sensitivity of 0.12%/V and a 320-ppb Allan Deviation floor for a 10-s stride. [ABSTRACT FROM AUTHOR]

This article presents an energy-efficient dual- $RC$ frequency reference intended for wireless sensor nodes. It consists of a digital frequency-locked loop (FLL) in which the frequency of a digitally controlled oscillator (DCO) is locked to a temperature-independent phase shift derived from two different $RC$ poly-phase filters (PPFs). Phase shifts with complementary temperature coefficients (TCs) are generated by using PPFs made from different resistor types (p-poly and silicided p-poly). The phase shift of each filter is determined by a zero-crossing (ZC) detector and then digitized by a digital phase-domain $\Delta \Sigma $ modulator ($\Phi $ - $\Delta \Sigma \text{M}$). The results are then combined in the digital domain via fixed polynomials to produce a temperature-independent phase shift. This highly digital architecture enables the use of a sub-1-V supply voltage and enhances energy and area efficiency. The 28-MHz frequency reference occupies 0.06 mm2 in a 65-nm CMOS process. It achieves a period jitter of 7 ps ($1\sigma $) and draws $142~\mu \text{W}$ from a 0.9-V supply, which corresponds to an energy consumption of 5 pJ/cycle. Furthermore, it achieves ±200 ppm inaccuracy from $- 40\,\,^\circ \text{C}$ to $85~^\circ \text{C}$ after a two-point trim. [ABSTRACT FROM AUTHOR]

In this paper a second order generalized integrator (SOGI) based quadrature signal generator (QSG) is proposed with the improved DC offset compensation parameter tuning procedure. Namely, for the conventional DC rejection technique, which comprises an integrator (I) included in the SOGI, the modified parameter tuning procedure is proposed based on the set QSG response damping factor value. In this way, when compared to existing QSG tuning techniques based on empirical trial-and-error approach, simplified parameter tuning procedure is proposed based on proposed parametric equations, which enable improved QSG performance verified by simulation and experimental runs by a single-phase phase-locked loop PLL. In this way the increased SOGI based QSG DC offset compensation speed can be achieved, which is critical in various types of single phase PLL applications.

Sliding discrete Fourier transform with kernel windowing technique is proposed for frequency estimation of periodic signals that can be applied to capacitance sensing. SDFT is an efficient technique to compute ${N}$ -point DFT of a signal by sliding the rectangular window one sample at a time. In the proposed work Hanning and Blackman windows replace rectangular window of SDFT to reduce the spectral leakage and increase the mainlobe width of the spectra. The concept of increased mainlobe width of the SDFT spectra has been exploited to increase the operating range of the frequency-locked loop. Kernels of these windows have been computed with certain coefficients and incorporated in the FLL to increase the operating range which increases the estimation input signal frequency. Designed FLL with Hanning window having bin index ${k} = 1$ estimates frequency from 4 to 56 kHz while with Blackman window estimates frequency from 6 to 75 kHz. The proposed scheme with kernel windowing has been implemented in FPGA and verified for enhanced performance. The experimental investigation on the proposed technique is validated for discrete capacitance sensing with maximum frequency estimation error of 0.054 and liquid level measurement of 0 - 13.5 cm with a sensitivity of 4.435 pF/mm. This method provides wide range of frequency estimation which results in wide range of capacitance measurement. [ABSTRACT FROM AUTHOR]

In this article, an improved grid synchronization method for three-phase grid-feeding converters using a dual enhanced second-order generalized integrator (eSOGI) frequency-locked loop (FLL) is proposed. The eSOGI, of which gains can be adjusted based on the positive-sequence component of the grid voltage, is designed to estimate the grid voltage accurately. Moreover, to improve the grid frequency estimation under grid voltage sags, frequency rate limits is suggested in the FLL structure. The selection of the eSOGI-FLL parameters is described as well. After the estimated grid voltages are obtained using the dual eSOGI-FLL, they are used to synthesize the references in the dual-current controllers for positive- and negative-sequence components. Through the simulation and experimental results under grid voltage sags and distorted grid conditions, the improved power control performance of the proposed method has been demonstrated in comparison with those of the existing methods. [ABSTRACT FROM AUTHOR]

This work proposes an interpretable radiomics approach to differentiate between malignant and benign focal liver lesions (FLLs) on contrast-enhanced ultrasound (CEUS). Although CEUS has shown promise for differential FLLs diagnosis, current clinical assessment is performed only by qualitative analysis of the contrast enhancement patterns. Quantitative analysis is often hampered by the unavoidable presence of motion artifacts and by the complex, spatiotemporal nature of liver contrast enhancement, consisting of multiple, overlapping vascular phases. To fully exploit the wealth of information in CEUS, while coping with these challenges, here we propose combining features extracted by the temporal and spatiotemporal analysis in the arterial phase enhancement with spatial features extracted by texture analysis at different time points. Using the extracted features as input, several machine learning classifiers are optimized to achieve semiautomatic FLLs characterization, for which there is no need for motion compensation and the only manual input required is the location of a suspicious lesion. Clinical validation on 87 FLLs from 72 patients at risk for hepatocellular carcinoma (HCC) showed promising performance, achieving a balanced accuracy of 0.84 in the distinction between benign and malignant lesions. Analysis of feature relevance demonstrates that a combination of spatiotemporal and texture features is needed to achieve the best performance. Interpretation of the most relevant features suggests that aspects related to microvascular perfusion and the microvascular architecture, together with the spatial enhancement characteristics at wash-in and peak enhancement, are important to aid the accurate characterization of FLLs. [ABSTRACT FROM AUTHOR]

A second-order generalized integrator (SOGI) is a resonant regulator with a pair of complex-conjugate poles, and therefore, with infinite magnitude at its center frequency. Thanks to this property, one can put together a set of $m$ SOGIs in an elegant way and decompose a single-phase signal into its constituent frequency components and detect their amplitude and phase angle. Such a configuration, which is often referred to as the multi-SOGI (MSOGI) structure, requires a frequency estimator to adapt the center frequency of SOGIs to frequency changes. This frequency estimation is often provided by interconnecting the MSOGI structure with a basic frequency-locked loop (FLL) or phase-locked loop (PLL). The resulting structures are known as the MSOGI-FLL and MSOGI-PLL. These structures and their close variants are mathematically difficult to analyze probably because of the lack of a linear model for these systems. This article aims to bridge this research gap. First, it is shown how linear time-periodic (LTP) models of the MSOGI-FLL and MSOGI-PLL can be obtained. The model verification, obtaining open-loop harmonic transfer function from the LTP model, and LTP stability assessment of MSOGI-based synchronization systems are the next parts of this article. Finally, some close variants of the MSOGI-FLL/PLL are considered and their modeling and stability assessment are briefly discussed. [ABSTRACT FROM AUTHOR]

In this paper, a novel closed-loop synchronization algorithm is proposed based on the linear phase angle detection. The linear phase detection is performed by the inverse tangent (atan2) trigonometric function, while the frequency tracking is performed by a proportional-integral (PI) loop filter and phase integrator. By using the linear phase detection, the linear phase-locked loop (PLL) is employed, which is simpler to implement and to tune, and which also performs better for large frequency and phase variations when compared to conventional PLL algorithms. Also, the novel technique operates consistently for a whole range of designated PLL crossover frequencies when compared to existing PLL techniques, which makes it a better candidate when higher filtering is required of higher harmonics and measurement noise. When compared with existing algorithms that use atan function for phase angle estimation, the novel algorithm enables the frequency estimation that does not include differentiation, which improves the resulting algorithm immunity to measurement noise and higher harmonics. The novel PLL is tested by simulation and experimental runs.

This article presents a robust single-phase phase-locked loop (PLL)-less frequency, phase, and amplitude estimation technique. The proposed scheme, unlike PLL approaches, does not require a rigorous design and tuning process in order to attain a better stability margin. It is important to note that an improved discrete-time oscillator is obtained by involving a comb filter, which helps improve the dc-offset rejection capability and transient response time. Moreover, the notch-filter-like behavior and the introduction of imaginary zeros ensure better harmonic removal ability when compared to a known nonadaptive discrete-time oscillator. The proposed scheme relies on an open-loop frequency estimation technique that does not involve an inverse trigonometric function for the estimation of fundamental frequency deviation. The feedbackless architecture of the scheme and the avoidance of inverse trigonometric function, therefore, assist in reducing the real-time implementation complexity. However, under off-nominal grid frequency deviations, the amplitude and the phase of the output of the prefilter will suffer from errors. These errors are compensated by employing a mathematical regression approach. The results are experimentally validated and compared in order to prove the robustness and usefulness of the proposed scheme for single-phase applications. [ABSTRACT FROM AUTHOR]

Phase-locked loops (PLLs) and frequency-locked loops (FLLs) are of importance in power and energy applications. Both technologies have been introduced to speed-sensorless- controlled motor drives, and increasing applications of PLLs and FLLs for speed estimation are foreseen. To enable a proper and good design, a thorough review of the PLL- and FLL-based speed estimation schemes is then provided in this article. It is revealed through the review that many PLL- and FLL-based estimation schemes fail to accurately track a frequency ramp (i.e., obvious estimation errors appear), which may lead to a compromised estimation accuracy when these schemes that are applied in induction motor drives operating during acceleration and deceleration processes. To address this, the proven speed estimation schemes together with new attempts are also presented in this article. Moreover, various challenges to the PLL- and FLL-based speed estimation schemes, including harmonics, dc offsets, and parameter variations, are considered when evaluating these schemes. Solutions to tackle these disturbances are accordingly presented. In addition, two representative estimation schemes are exemplified through experimental tests. Finally, further challenges in using the PLL- and FLL-based schemes for speed estimation are discussed. [ABSTRACT FROM AUTHOR]

The complex and ever-changing harmonics in grid voltage will cause performance deterioration of the frequency-locked loops (FLLs). Although various measurements had been adopted to attenuate the deterioration, they had to make the tradeoff between the dynamic and steady-state characteristics generally. Consequently, a novel single-phase FLL that can adaptively adjust the dynamic and steady-state performance was proposed in this article. The proposed FLL regards the damping ratio of second-order generalized integrator-FLL (SOGI-FLL) as a time-varying parameter rather than a constant, and adjusts the damping ratio adaptively, so the proposed FLL was named SOGI-FLL with damping ratio adaptation (DASOGI-FLL). The adaptive mechanism is to decrease the damping ratio as frequency estimation error decreases and vice versa. To realize the mechanism, a novel variable was constructed to indirectly correlate the damping ratio with frequency estimation error. An objective function containing the constructed variable for damping ratio adaptation was designed, and the adaptive algorithm was derived by using the gradient ascent method. Then, the convergence analysis, parameter design, and digital implementation of the algorithm were elaborated. Finally, the results of simulation and experiment reveal that, benefits from the damping ratio adaptation, DASOGI-FLL can achieve rapid convergence, strong filtering capability, and high estimation accuracy simultaneously. [ABSTRACT FROM AUTHOR]

This brief reports a high-performance, low-power temperature sensor suitable for wireless IoT devices/RFID tags. The system utilizes a mostly digital approach to achieve energy-efficient, sub- $\mu \text{W}$ operation with a resistor-based temperature sensor. A sampled, incomplete-settling, switched-capacitor-based Wheatstone bridge is read out using a digital frequency-locked loop (DFLL) while harnessing the quasi-periodic limit cycles to reduce in-band noise. Implemented in a 65 nm CMOS process, it consumes 310 nW and achieves 9.8 mK resolution in a 10 ms conversion time. This results in a 297 fJ ${\mathrm {\cdot }}\text{K}~^{2}$ figure-of-merit (FoM) and low energy (3.1 nJ/meas.). [ABSTRACT FROM AUTHOR]

This article presents an iterative frequency lock loop (FLL)-assisted-phase lock loop (PLL) (FPLL) design in state space according to the minimum mean square error criterion. This is achieved by constructing a high fidelity carrier signal model with the consideration of the non-Gaussian nonwhite measurement noise characteristics. Two popular arctangent discriminators, e.g., two-quadrant (Atan) and four-quadrant (Atan2) are used to produce the PLL and FLL measurements for FPLL, respectively. The filter gain is selected to minimize the trace of the error covariance matrix and an iteration approach to quickly compute the steady-state filter gain is introduced. The nonlinearity in the discriminator and filter behaviors in FPLL at low $C/N_0$ and high dynamic conditions are investigated. The closed-form expressions of the closed-loop transfer function as well as error transfer function are clarified. The thermal noise induced tracking jitters on each carrier state, e.g., phase, doppler, and doppler rate, are derived, analyzed, and verified via Monte Carlo simulation, accordingly. The theoretical properties show that the iterative FPLL achieves the following. 1) The comparable tracking performance to the well-designed PLL-only. 2) The enhanced tracking accuracy over the well-designed FLL-only. 3) The improved tracking sensitivity over the conventional Kalman filter-based FPLL (KF-FPLL), at low $C/N_0$ condition and high dynamic conditions. [ABSTRACT FROM AUTHOR]

This brief describes an integer-N-type-II sub-sampling phase-locked loop (SS-PLL) incorporating a push–pull sub-sampling phase detector to significantly suppress the spur-induced binary frequency shift keying modulation (BFSK) effect and a low-power fast-locking frequency-locked loop (FLL) to shorten the settling time. Prototyped in 65-nm CMOS, the SS-PLL at 3.3 GHz shows a reference spur of −82.2 dBc, an integrated jitter of 64.9 fsrms (1 kHz to 40 MHz), and an in-band phase noise (PN) of −128.4 dBc/Hz at 1-MHz offset. The corresponding jitter power figure of merit (FOM) is −255 dB. The entire SS-PLL consumes 7.5 mW, with only $90~\mu \text{W}$ associated with the FLL. [ABSTRACT FROM AUTHOR]

This article proposes a circuit architecture and design strategy of a low-noise oscillator based on the distributed RC network. The distributed RC network receives a differential step input and propagates the true phase through the resistive path while the complementary phase through the capacitive path. It effectively suppresses the effect of noise by increasing the signal transition slope at the time of interest. It is achieved by embedding a bandpass characteristic with a phase delay of $\pi $. A 358-kHz quadrature oscillator with a fourth-stage RC network is implemented using the 0.18- $\mu \text{m}$ CMOS process. It achieves an figure of merit (FoM) of −161.2 dBc/Hz at a 100-Hz offset with a stable 20-dB roll-off in the phase noise and an Allan deviation floor of less than 0.7 ppm. [ABSTRACT FROM AUTHOR]

This article presents a wide-lock-in-range and ultralow-jitter, 12–14.5 GHz subsampling phase-locked loop (SSPLL) using a frequency-disturbance-detecting/correcting (FDC) loop. By detecting and correcting the frequency disturbance, $f_{\mathbf {D}}$ , frequently, the FDC loop can increase the lock-in range of the SSPLL to 3.2 times the reference frequency, $f_{\mathbf {REF}}$. Since the FDC loop only is concerned with correcting an $f_{\mathbf {D}}$ -event at the output and is not concerned with the jitter, there is no design tradeoff between the jitter, and the power consumption as is the case in previous techniques. Due to its logic using frequency information rather than phase, the FDC loop also can reduce the time required for the reacquisition of the frequency. In this work, the prototype SSPLL was fabricated in a 65 nm CMOS, and it used the 50 MHz $f_{\mathbf {REF}}$. In the measurements, the FDC loop that consumed only 150 $\mu \text{W}$ of power made the SSPLL achieve the lock-in range of 160 MHz and the frequency-reacquisition time of less than 800 ns. The measured rms jitter at 13 GHz was 83 fs. The active area was 0.23 mm2, and the total power consumption was 7.7 mW. [ABSTRACT FROM AUTHOR]

This article presents a millimeter-wave (mmW) frequency synthesizer based on a new charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge sharing with a resonant LC-tank for phase correction, while the resulting charge residue on the sharing capacitor is processed by a digital frequency-tracking loop (FTL) against the process, voltage, and temperature (PVT) variations. Furthermore, a general phase noise (PN) theory of CSL, with injection locking (IL) being a special case, is proposed based on a unified multirate ${z}$ -domain model, supporting any frequency division ratio ${N}$ and CSL (or IL) strength $\beta $. The new theory sheds light not only on all IL-like PN phenomena (chiefly, its “loop” bandwidth being up to half of the reference frequency, and the oscillator PN increasing 3 dB beyond the “loop” cutoff frequency) but also on how to choose the CSL bandwidth via the sharing capacitor in order to optimize the rms jitter performance. The prototype in 28-nm CMOS achieves 77-fs rms jitter in 21.75—26.25 GHz while consuming 16.5 mW for mmW quadrature frequency generation. [ABSTRACT FROM AUTHOR]

A novel frequency‐to‐voltage converter based phase‐locked loop (PLL) is proposed to overcome the inability of a frequency‐to‐voltage converter based frequency‐locked loop to lock phase. The proposed dual‐loop PLL adds variable phase‐locking capability, such that the phase locking angle can vary from 0–360°. The additional variable phase‐locking can be applied in data communication in the form of phase modulation. The design is targeted for a 0.5‐μm CMOS process. The proposed design generates a 480 MHz clock from a reference clock of 15 MHz. In simulation, the proposed PLL locks within 3.56 μs while consuming 1.61 mW of power. [ABSTRACT FROM AUTHOR]

This article presents a fast phase-locking and amplitude detection scheme for single-phase applications. The proposed scheme employs a pseudo-rectification process in order to generate even harmonics from the grid signal. The dc-offset component present in the grid signal increases the sensitivity of the pseudo-rectification process, and the design of the prefiltering stage must, therefore, be completely focused on the rejection of dc-offset and the even-harmonics. The application of a half-cycle (HC) prefilter would consequently appear to be a highly attractive option as regards improving the dynamic response time and even harmonic rejection abilities. However, the elimination of the dc-offset component and the estimation of phase and amplitude information is still a very challenging task. The aforementioned issues are addressed by employing an HC comb filter and an HC nonadaptive Lyapunov orthogonal signal generator. The estimation of single-phase grid parameters is thereby made simpler by employing an improved open-loop frequency estimation, which is capable of providing accurate frequency deviation information with good precision. The research shown herein also reveals that the estimation of the amplitude and phase information differs slightly from the usual mathematical notations owing to the pseudo-rectification method adopted in the proposed work. Note that the prefiltering stage is nonadaptive in nature, which may lead to steady-state errors in the amplitude and phase information under off-nominal frequency conditions. An online mathematical correction approach dependent on frequency deviation is, therefore, employed in order to obtain the error-free amplitude and phase information. Finally, the robustness of the current proposal is validated by experimentally comparing several known grid parameter estimation schemes using a real-time controller. [ABSTRACT FROM AUTHOR]

The fixed-length transfer delay-based adaptive frequency-locked loop (TD-AFLL) has drawn much attention due to its concise structure and faster response speed than conventional second-order generalized integrator-based FLL. However, the application of TD-AFLL is still limited owing to the poor performance in terms of phase-angle/amplitude detection under distorted grid conditions. This paper explores an inherent input-output relationship of TD-AFLL, and a notch filter is employed to represent its filtering feature. Then a high-order filter is designed based on this notch filter, and an enhanced TD-AFLL (ETD-AFLL) with improved phase-angle/amplitude detection is further derived. The ETD-AFLL highly improves the phase-angle/amplitude detection accuracy under distorted grid conditions yet keeps the same fast response speed as TD-AFLL. In addition, the ETD-AFLL only requires a slightly additional computational cost. Experimental results are given to support the proposed ETD-AFLL. [ABSTRACT FROM AUTHOR]

In this article, a resilient enhanced second-order generalized integrator with frequency locked loop and inner loop filter (ESOGI-FLL-WIF) control algorithm is implemented to enhance the power quality and to regulate the voltage/frequency of a microgrid. This control has a simple structure, fast convergence, and excellent dynamic and steady-state response. The ESOGI-FLL-WIF control algorithm is used for assessing the fundamental constituent from harmonics and dc bias infected current. ESOGI-FLL-WIF control strategy tracks the frequency and tunes to the frequency fluctuations in transient situations. To have a fair comparison, the performance of the ESOGI-FLL-WIF control algorithm is compared with already existing controls. This three-phase four-wire islanded system consists of a solar photovoltaic array and pico-hydro turbine-driven synchronous reluctance generator (SyRG). As an alternative to the conventional generators, SyRG is used because it is economical (no permanent magnets in the rotor) and has high efficiency (no electrical losses in the rotor). The four-leg converter compensates neutral current and controls the reactive power injection under unbalance load condition, whereas for active power management, battery energy storage is incorporated in the system. A prototype of the system is developed and tested under different situations of load unbalancing and solar insolation change to confirm the effectiveness and viability of the control strategy. [ABSTRACT FROM AUTHOR]

Contrast-enhanced ultrasound (CEUS) is generally employed for focal liver lesions (FLLs) diagnosis. Among the FLLs, atypical hepatocellular carcinoma (HCC) is difficult to distinguish from focal nodular hyperplasia (FNH) in CEUS video. For this reason, we propose and evaluate a feature fusion method to resolve this problem. The proposed algorithm extracts a set of hand-crafted features and the deep features from the CEUS cine clip data. The hand-crafted features include the spatial-temporal feature based on a novel descriptor called Velocity-Similarity and Dissimilarity Matching Local Binary Pattern (V-SDMLBP), and the deep features from a 3-D convolution neural network (3D-CNN). Then the two types of features are fused. Finally, a classifier is employed to diagnose HCC or FNH. Several classifiers have achieved excellent performance, which demonstrates the superiority of the fused features. In addition, compared with general CNNs, the proposed fused features have better interpretability. [ABSTRACT FROM AUTHOR]

Nanomechanical resonant sensors that are based on detecting and tracking the resonance frequency deviations due to events of interest are being advocated for a variety of applications. All sensor schemes currently in use are subject to a basic trade-off between accuracy and speed, while there is great interest in improving both in order to enable unprecedented and widespread applications. Based on a thorough understanding of the characteristics of current resonant sensor architectures, we propose adaptive and flexible sensor schemes. Unlike recently proposed time-resolved mechanical detection methods, the proposed schemes do not require ensemble averaging of the resonator response for many independent identical stimuli. Distinct one-time events can be detected in real-time with high time resolution with an accuracy that then improves considerably with elapsed time. While the proposed adaptive schemes also need to abide by the fundamental speed versus accuracy trade-off, we show that there is still “some room at the bottom” for improvement with sensor architecture innovations. Pareto optimal performance that reaches a bound that is imposed by the fundamental thermomechanical noise can be achieved. [ABSTRACT FROM AUTHOR]

This letter presents a 2.5-D frequency selective surface (FSS) based on four-legged loaded loop elements of third-order iteration inspired by fractal geometries. This FSS design strives to harness the efficacy of the space-filling property of fractals and an additional degree of freedom associated with the use of metal vias in planar structures to obtain a miniaturized unit cell by enhancing the electrical length altogether. The proposed FSS provides a band-stop response with resonance at 1.056 GHz and demonstrates identical transmission curves for transverse-electric and transverse-magnetic modes of polarization of the incident wave. The unit cell of the proposed FSS achieves a figure-of-merit (λ0/P) = 29, where λ0 is the free space resonant wavelength and P is the periodicity exhibited by the unit cell, and offers an excellent angular stability up to 75° for oblique incidence. The measured results advocate the real-time shielding effectiveness of the fabricated prototype. [ABSTRACT FROM AUTHOR]

To improve the filtering capability of frequency-locked loop (FLL), the high-order bandpass filters FLL was proposed recently. This article proposes a high-order FLL in synchronous (dq) reference frame where the high-order low-pass filter is adopted. A general analytical model is established for the high-order FLL. Based on the model, it is proven that the conventional high-order FLL exhibits no improvement in terms of filtering ability of the frequency estimation. Based on this analysis, a new frequency estimation loop is proposed to obtain an enhanced filtering capability for the FLL. Additionally, the proposed high-order FLL has the advantage of simple implementation compared to conventional high-order FLLs. A design example is then demonstrated and simulated to show the accuracy of the model and the effectiveness of the proposed FLL. Finally, the proposed high-order FLL is experimentally verified on a testbed using a 32-bit floating-point DSP TMS320F28379D at 200 MHz. [ABSTRACT FROM AUTHOR]

In the electrical power and energy (EPE) area, the traditional concept in designing the synchronization system of power converters is using the phase-locked loop (PLL) concept. An alternative way is using the frequency-locked loop (FLL) concept, which is also known as the adaptive notch filter, adaptive noise cancelation technique, gradient descent estimator, adaptive observer, D-estimation method, and transformation angle detector, among others names. Along with the increased popularity and application of FLLs in EPE systems, the misconception about this design concept is growing. To be more exact, most EPE research communities introduce FLLs as synchronization systems of different properties compared to PLLs. This article aims to explain the main reasons behind this misconception and contribute to dispelling it. [ABSTRACT FROM AUTHOR]

This article focuses on the control based on an extended second-order generalized integrator with a frequency locked loop (Ext-SOGI-FLL) to provide satisfactory performance for synchronization of microgrid (MG). In the existing phase-locked loop (PLL) based control, the loop filter used is not capable to entirely remove harmonics. Hence, the harmonics in voltage considerably affect the frequency as well as phase extraction, both in the dynamics and steady-state situations. To deal with this problem in this system, the voltage source converter is controlled using Ext-SOGI-FLL. This control algorithm extracts the fundamental voltage and current for assessment of phase angle and reference source current (maintaining the required IEEE power quality standard-519 & 1547). This FLL-based control is also capable of estimating the exact frequency and phase magnitude, which suffer from phase offset due to frequency change. The comparative results validate that the response of Ext-SOGI-FLL control in comparison to the existing control algorithms is faster at loads and generation perturbations. Simulated and test results for MG system combining a solar photovoltaic, pico-hydropower generation, and battery validate its performance while feeding local loads uninterruptedly. [ABSTRACT FROM AUTHOR]

The renewable energy sources are intermittent in nature with high availability-based uncertainties. These resources when integrated to the utility grid significantly hinder the grid power quality (PQ). This article deals with PQ issues arising in the topology including the grid connected renewable energy generating system, which is a combination of wind turbine (WT) driving the synchronous generator (SG) and solar photovoltaic (PV) array and control strategies to improve the same. The solar PV array is associated at the dc link eliminating the dc–dc converter stage via a common dc link. The variable revolutions per minute (RPM) operation is achieved by the back to back connected grid side VSC (GVSC) and the machine side voltage source converter (MVSC). The GVSC is controlled by using the nonlinear harmonic observer (NHO) control. It provides robust implementation at various perturbations faced practically, i.e., discontinuous jump of frequency, phase, and amplitude. The fundamental load current component is effectively extracted. The NHO control is deployed within the framework to allow the system to dynamically adapt to the changes in the operating environment while maintaining the PQ of the utility grid. A special attention is paid to the condition when the power generated by the solar PV array is zero (during night operation) and the GVSC acts in the distribution static compensator (DSTATCOM) mode fulfilling the reactive power requirement. The regulation of MVSC is achieved by the vector control. Independent optimal power extraction techniques are featured for both wind and solar PV array. Test conditions are realized on the laboratory developed prototype and test results are acquired for PQ, loss of supply from solar PV array, effects of randomness of the wind speed, and solar insolation along with load alterations. [ABSTRACT FROM AUTHOR]

Most conventional vital-sign radars cannot easily detect human vital sign signals under nonperiodic body movement. This article presents a novel frequency-locked loop (FLL) radar that can track the phase changes that are caused by nonperiodic body movement. A gain/phase detector and a cross correlation function (CCF) in the FLL radar greatly reduce the second harmonic, the intermodulation terms between vital sign signals and nonperiodic body movement noise, enhancing both the signal-to-noise ratio and the accuracy of detection of the vital signs. Measurements indicated that the implemented 2.4-GHz FLL radar with a gain/phase detector and CCF can effectively detect the human respiration rate (RR) and heart rate (HR) under nonperiodic body movement. Using a chest belt as the measurement reference, the standard deviation (SD) of RR and HR measurements were 1.27 and 5.69 beats/min, respectively, when the seated subject under test (SUT) swung nonperiodically his upper body. When the SUT walked away from the radar naturally at 2.6 km/h, the implemented FLL radar measured RR and HR with SDs of 2.67 and 8.28 beats/min, respectively. [ABSTRACT FROM AUTHOR]

This article presents a super twisting sliding-mode control (ST-SMC) for single-phase dynamic voltage restorers (DVRs). Unlike the conventional first-order sliding-mode controller, the proposed ST-SMC technique eliminates the need for differentiating the compensation voltage in the sliding surface function while keeping the merits of first-order SMC. As a consequence of employing ST-SMC, a continuous control signal is achieved from which the pulsewidth modulation (PWM) signals can be generated. In this case, the inverter operates at a constant switching frequency. The stability analysis of ST-SMC is also presented. The reference compensation voltage needed in ST-SMC is estimated by using Brockett oscillator-based frequency-locked loop. Theoretical considerations are verified through experimental results under ideal and distorted grid voltage conditions. The obtained results show that the ST-SMC has good dynamic performance and can maintain the load voltage at a desired level under voltage sag, swell, and harmonically distorted grid voltages. [ABSTRACT FROM AUTHOR]

In this article, a modified reduced order generalized integrator-based frequency-locked loop (MROGI-FLL) is proposed for controlling the interfacing inverter of the grid-tied photovoltaic system to mitigate the harmonics. Additionally, a fuzzy tuned PID controller is integrated in the proposed scheme to minimize the steady-state error, which results the voltage level is maintained constant at the common dc-link bus terminals. The MROGI-FLL is designed to evaluate the three-phase reference currents by extracting the fundamental constituents from the load currents and grid voltages. The proposed MROGI-FLL has several advantages such as better harmonic mitigation capability, control adaptivity, adaptive frequency and phase, grid synchronization, and low computation burden. The proposed reference current generator is simulated on MATLAB/Simulink platform under steady state and various transient conditions.The comparative study of proposed scheme is compared with the existing and adaptive control techniques, which assures the potency of the proposed control algorithm in-terms of harmonic mitigation, dc-offset rejection, frequency variation, and computation burden. Finally, the experimental results are verified through an experimental platform by using the dSPACE evaluation kit and both the simulation and hardware characteristics are well justified to the IEEE-519 standard limits. [ABSTRACT FROM AUTHOR]

There are two bias schemes, namely current-bias and voltage-bias, for the directly coupled readout circuit of direct current superconducting quantum interference device (dc SQUID). In order to find out the difference between two bias schemes, we present the theoretical analyses on their equivalent circuits, working point locations, and noise performances. The theoretical analysis and experimental validation prove that the voltage-bias scheme achieves a larger transfer coefficient and exhibits a better noise performance than the current-bias scheme in the reading of conventional dc SQUID. [ABSTRACT FROM AUTHOR]

The presence of dc offsets results in fundamental frequency oscillations in the frequency estimation and it is a challenging problem in single-phase grids. In this article, a four consecutive samples (4CSs) based method is proposed to estimate grid frequency with strong dc offset rejection capability. In details, a 4CS model is established based on the relationship among the fundamental grid voltage, dc offsets, and their consecutive sample signals. Different from the traditional 3CS model, the proposed 4CS model can reject the negative effects of dc offsets completely. Based on the obtained model, a frequency estimation is proposed and stability analysis is provided according to the adaptive control theory. Unlike the traditional 3CSs relying on prefilters, the proposed method is filter-free and it still has strong suppression capability against dc offsets. The theoretical sound and experimental results indicate that the proposed method achieves accurate frequency estimation with good dc offset rejection capability. [ABSTRACT FROM AUTHOR]

Second-order Generalized Integrator (SOGI)-based quadrature-signal-generator (QSG) together with either a phase-locked-loop (PLL) or a frequency-locked-loop (FLL) constitute two types of typical synchronization units (i.e., SOGI-PLL and -FLL) that have been widely used in grid-tied converter systems. This article will reveal and clarify the stability issue of these two synchronization units arising from different implementations of the frequency-feedback-path (FFP) connecting the SOGI-QSG and the PLL/FLL. In this regard, four types of FFP implementations will be discussed. Although different implementations of the FFP will not affect the steady-state frequency adaptation, their dynamical effects on the small-signal stability of SOGI-PLL/FLL remain concealed. To this end, this article will present a comprehensive stability assessment and comparative analysis of SOGI-PLL/FLL focusing on the FFP issue. To extend the applicability and accuracy of discussions, all the analyses will be fulfilled by using a parameter space-oriented stability assessment method formulated in the linear-time periodic (LTP) framework. The obtained results are verified by time-domain simulations, and the main findings are further interpreted by using appropriate analytical models. [ABSTRACT FROM AUTHOR]