Search

Your search keyword '"Fu, Haipeng"' showing total 199 results
Start Over Author "Fu, Haipeng"
199 results on '"Fu, Haipeng"'

10. A high linearity 0.05–7 GHz digital step attenuator with the capacitive compensation for bonding wires parasitic parameters.

Author

Fu, Haipeng, Tao, Jiqing, Hu, Jianquan, Wang, Keping, and Ma, Kaixue

Subjects
*ROOT-mean-squares, *INSERTION loss (Telecommunication), *WIRE
Abstract

This paper presents a broadband, high linearity 7‐bit digital step attenuator (DSA) using a low‐cost bonding wire package. Capacitive compensation technique is proposed to offset the deterioration of attenuation accuracy and operating bandwidth caused by the parasitic parameters of the bonding wire and switching transistors. And the negative voltage bias technique (NVBT) is proposed to improve the linearity of the DSA. Based on the capacitive compensation technique and the NVBT, a 7‐bit DSA is implemented using a 0.13 µm Silicon‐On‐Insulator (SOI) process with a low‐cost bonding wire package. The DSA achieves broadband operation with an insertion loss (IL) of 2.7 dB at 7 GHz and root mean square (RMS) amplitude error less than 0.5 dB at DC‐7 GHz. The input P1 dB of all states is better than 31.7 dBm. [ABSTRACT FROM AUTHOR]

Published
2024
Full Text
View/download PDF

13. A Compact 140-GHz Power Amplifier With 15.4-dBm Psat and 14.25% Peaking PAE in 28-nm Bulk CMOS Process

Author

Zhang, Lei, Ma, Kaixue, Fu, Haipeng, Wang, Yongqiang, Wang, Keping, Meng, Fanyi, and Li, Xuguang

Abstract

This article presents a fully integrated high-power and high-efficiency $D$ -band power amplifier (PA) with two-way differential power combining in a 28-nm bulk CMOS process. The overall performance improvement is achieved mainly from three aspects. First, the effect of resistance brought by the actual matching network on performance above 100 GHz is considered in transistor selection, and the deoverstabilization technique is proposed to select structures with high output power and high efficiency at stabilization. Meanwhile, the compensating inductors are introduced in the distributed active transformer (DAT) network to reduce RF signal leakage and insertion loss of the power combiner. Finally, considering the low intrinsic transistor gain above 100 GHz in CMOS, the effect of different interstage matching network losses on the overall efficiency is analyzed to guide the optimization objectives of different matching networks, taking into account both gain and chip area. The three-stage four-way power combining PA achieves a peak gain of 19.2 dB, a measured maximum saturated output power of 15.4 dBm, a peak power-added efficiency (PAE) of 14.25%, and a high power density of 381 mW/mm2. To the best of our knowledge, the proposed PA achieves the highest PAE in bulk CMOS-based ${D}$ -band PAs with an output power greater than 15 dBm.

Published
2024
Full Text
View/download PDF

14. A 34.16–39.6 GHz low phase noise VCO for frequency‐modulated continuous‐wave radar in a 28‐nm CMOS.

Author

Fu, Haipeng, Yuan, Fenglin, and Ma, Kaixue

Subjects
*PHASE noise, *VOLTAGE-controlled oscillators, *RADAR, *CAPACITOR banks, *CAPACITOR switching
Abstract

A dual‐core voltage‐controlled oscillator (VCO) using harmonic resonance is presented in this letter. Without an additional switch capacitor bank, harmonic resonance implemented in VCO is realized by only a single control voltage, satisfying the requirement of frequency‐modulated continuous‐wave radar. Two pairs of varactors are added to the transformer‐based tank, which ensures a constant ratio between the two resonant frequencies of the tank in the entire tuning range. Robustly single‐frequency oscillation is obtained by increasing the coupling coefficient of the transformer and the coupling capacitor's capacitance. Implemented in a 28‐nm complementary metal–oxide–semiconductor, the VCO shows a 14.75% frequency tuning range covering 34.16–39.6 GHz. The measured results show it exhibits −102.13 dBc/Hz phase noise at a 1 MHz offset from the 34.16 GHz. The oscillator core draws 21–28 mA from a 0.9 V supply. [ABSTRACT FROM AUTHOR]

Published
2023
Full Text
View/download PDF

20. A Reconfigurable Injection-Locked LO Generator With a Wideband-Harmonic-Shaping Class-F23 VCO for Multibands 5G mm-Wave

Author

Wang, Zhipeng, Ma, Kaixue, Ma, Zonglin, Shi, Hao, Fu, Haipeng, and Xu, Jiangtao

Abstract

A reconfigurable injection-locked local oscillator (RE-ILO) generator that leverages a multitanks wideband-harmonic-shaping Class-F23 voltage-controlled oscillator (VCO), a RE injection-locked frequency multiplier (RE-ILFM), and a power-efficient injection-locked frequency amplifier (ILFA) for multiple fifth-generation (5G) millimeter-wave (mm-wave) bands is hereby presented. For the VCO, an inductive multiplier inside the positive feedback loop boosts the drain-to-gate voltage gain (Av). Besides, a source-inductive loaded on the output buffer, coupled with a separated inductor, is feedback to the drain of the cross-coupled transistors to expand the impedance peak at the 3rd harmonic for a small fluctuation of 1/ $f^{3}$ phase noise (PN) corner over the entire tuning range (TR). The measured results of the VCO prototype in 55-nm CMOS achieved the VCO measures a TR of 10.65–14.37 GHz, i.e., 29.74%. The FOM $_{T}$ is 192.2 dBc/Hz and the 1/ $f^{3}$ PN corner is 380 ± 100 kHz. Additionally, a RE-ILFM with both frequency $\times 2$ doubler mode (DM) and $\times 3$ tripler mode (TM) is introduced to expand the operation band of the VCO. The ILFA is cascaded for harmonic rejection and power improvement. The proposed RE-ILO generator achieves a frequency TR from 22.25 to 28.61 GHz, i.e., 25% and 35.9–42.04 GHz, i.e., 15.75% with a 1-MHz-offset PN from −102.78 to −104.1 dBc/Hz at DM, −98.48 to −100.67 dBc/Hz at TM, and consumes 66 mW power with an output power of 1.3 dBm.

Published
2023
Full Text
View/download PDF

23. LncRNA-Smad7 mediates cross-talk between Nodal/TGF-β and BMP signaling to regulate cell fate determination of pluripotent and multipotent cells

Author

Kong, Xiaohui, primary, Yan, Kun, additional, Deng, Pujuan, additional, Fu, Haipeng, additional, Sun, Hongyao, additional, Huang, Wenze, additional, Jiang, Shuangying, additional, Dai, Junbiao, additional, Zhang, Qiangfeng Cliff, additional, Liu, Jun-jie Gogo, additional, and Xi, Qiaoran, additional

Published
2022
Full Text
View/download PDF

38. Design of a Compact SISL BPF With SEMCP for 5G Sub-6 GHz Bands

Author

Kaixue Ma, Hao Zhang, Zhang Wenwen, and Fu Haipeng

Subjects
Physics, business.industry, 020206 networking & telecommunications, 02 engineering and technology, Condensed Matter Physics, Topology, Inductive coupling, Resonator, Band-pass filter, Filter (video), 0202 electrical engineering, electronic engineering, information engineering, Wireless, Multi-band device, Electrical and Electronic Engineering, business, Passband, 5G
Abstract

In this letter, a cross-coupled dual-bandpass filter (BPF) with separate electric and magnetic coupling paths (SEMCPs) for 5G sub-6 GHz applications is proposed. Source-to-load couplings are also introduced in this structure for the flexibility of heterogeneous feed lines. Five controllable transmission zeros (TZs) in total are produced in the dual-band filter. The filter achieves good overall performance by adopting two pairs of quarter-wavelength stepped-impedance resonators (SIRs). To minimize the size of the filter and enlarge the controllable range of the second passband, the SIRs forming the second passband are separated and folded onto two different layers. The measured dual band filter achieves fractional bandwidths of 7.82% and 4.08%, centered at frequencies of 3.45 and 4.9 GHz with insertion losses of 1.15 and 1.42 dB, respectively.

Published
2020

50. A 24.4~39.6 GHz Wide Locking Range Divide-by-4 Injection-Locked Frequency Divider With High Harmonic Rejection Ratio

Author

Fu, Haipeng, Zhao, Lanfei, Wang, Zhipeng, and Ma, Kaixue

Abstract

In this brief, an innovative divide-by-4 injection-locked frequency divider (ILFD) is hereby proposed to expand the locking range (LR) and improve the harmonic rejection ratio (HRR). Specifically, a fourth-order transformer-based resonator is adopted to improve the LR without any additional tuning capacitors, and a dual-tank network is proposed to optimize the harmonic rejection. To implement the proposed techniques, two chips with different networks are analyzed, designed, and fabricated in a 28-nm CMOS technology. The chip with the dual-tank network is proven to achieve the bandwidth from 24.4 to 39.6 GHz, i.e., 47.5% with the second and third harmonic rejection ratios of better than 32 dBc and 11 dBc, while the other chip achieves the bandwidth from 30.8 to 42.6 GHz, i.e., 32.2%. Additionally, the ILFD with the dual-tank network is confirmed to possess differential output power from −17.5 to −19.8 dBm, consuming only 7.4 mW dc power under a 0.5-V supply.

Published
2023
Full Text
View/download PDF

Catalog

Books, media, physical & digital resources
See catalog results