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A proposed media-processor architecture, which is appropriate for MPEG-4 natural and synthetic video decoding, was developed. The architecture focused on the functional module for inverse discrete cosine transform (IDCT) and a geometrical transformer. Its distinct feature is that four matrix-vector multipliers can carry out matrix-vector multiplications required in the geometrical transformation of 3-D computer graphics for synthetic video objects and in the IDCT for natural video objects.

In designing VLSI, the problem of bow large the chip area will be is of considers able interest. Thus, the primary objective in investigating this problem is to consider formally processing elements and wires of a circuit to be vertices and edges of an undirected graph, and then clarify the area sufficient or necessary to embed this graph onto a rectangular grid graph according to a certain enbedding method (this is called an embedding model). In this paper, vertices correspond to a rectangular graph such that [length of long side]/[length of short side] ≤ constant, It is shown that under an embedding model, which forbids images of edges (wires) from passing through the inside of the vertex region of the rectangle, the maximum lower bound of the area corresponding to a general n-vertex d-degree graph is Χ(d²n²). As the result, it is seen that the conventionally known upper bound O(d²n²) cannot be improved any further as long as all n-vertex d-degree graphs are considered. [ABSTRACT FROM AUTHOR]