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44 results on '"Garcia-Herrero, Francisco"'

1. Low-Complexity Linear Programming Based Decoding of Quantum LDPC codes

Author

Javed, Sana, Garcia-Herrero, Francisco, Vasic, Bane, and Flanagan, Mark F.

Subjects
Computer Science - Information Theory
Abstract

This paper proposes two approaches for reducing the impact of the error floor phenomenon when decoding quantum low-density parity-check codes with belief propagation based algorithms. First, a low-complexity syndrome-based linear programming (SB-LP) decoding algorithm is proposed, and second, the proposed SB-LP is applied as a post-processing step after syndrome-based min-sum (SB-MS) decoding. For the latter case, a new early stopping criterion is introduced to decide when to activate the SB-LP algorithm, avoiding executing a predefined maximum number of iterations for the SB-MS decoder. Simulation results show, for a sample hypergraph code, that the proposed decoder can lower the error floor by two to three orders of magnitude compared to SB-MS for the same total number of decoding iterations., Comment: Accepted for publication at the IEEE International Conference on Communications (ICC) 2024

Published
2023

2. Check-Agnosia based Post-Processor for Message-Passing Decoding of Quantum LDPC Codes

Author

Crest, Julien du, Garcia-Herrero, Francisco, Mhalla, Mehdi, Savin, Valentin, and Valls, Javier

Subjects
Quantum Physics
Abstract

The inherent degeneracy of quantum low-density parity-check codes poses a challenge to their decoding, as it significantly degrades the error-correction performance of classical message-passing decoders. To improve their performance, a post-processing algorithm is usually employed. To narrow the gap between algorithmic solutions and hardware limitations, we introduce a new post-processing algorithm with a hardware-friendly orientation, providing error correction performance competitive to the state-of-the-art techniques. The proposed post-processing, referred to as check-agnosia, is inspired by stabilizer-inactivation, while considerably reducing the required hardware resources, and providing enough flexibility to allow different message-passing schedules and hardware architectures. We carry out a detailed analysis for a set of Pareto architectures with different tradeoffs between latency and power consumption, derived from the results of implemented designs on an FPGA board. We show that latency values close to one microsecond can be obtained on the FPGA board, and provide evidence that much lower latency values can be obtained for ASIC implementations. In the process, we also demonstrate the practical implications of the recently introduced t-covering layers and random-order layered scheduling.

Published
2023
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3. Layered Decoding of Quantum LDPC Codes

Author

Crest, Julien Du, Garcia-Herrero, Francisco, Mhalla, Mehdi, Savin, Valentin, and Valls, Javier

Subjects
Quantum Physics
Abstract

We address the problem of performing message-passing-based decoding of quantum LDPC codes under hardware latency limitations. We propose a novel way to do layered decoding that suits quantum constraints and outperforms flooded scheduling, the usual scheduling on parallel architectures. A generic construction is given to construct layers of hypergraph product codes. In the process, we introduce two new notions, t-covering layers which is a generalization of the usual layer decomposition, and a new scheduling called random order scheduling. Numerical simulations show that the random ordering is of independent interest as it helps relieve the high error floor typical of message-passing decoders on quantum codes for both layered and serial decoding without the need for post-processing.

Published
2023

9. Efficient Low-Latency Multiplication Architecture for NIST Trinomials With RISC-V Integration

Author

Imana, Jose L., Pinuel, Luis, Kuo, Yao-Ming, Ruano, Oscar, and Garcia-Herrero, Francisco

Abstract

Binary extension field arithmetic is widely used in several important applications such as error-correcting codes, cryptography and digital signal processing. Multiplication is usually considered the most important finite field arithmetic operation. Therefore efficient hardware architectures for multiplication are highly desired. In this brief, a new architecture for multiplication over finite fields generated by irreducible trinomials $f(x) = x^{m}+x^{t}+1$ is presented. The architecture here proposed is based on the use of a polynomial multiplier and a cyclic shift register that can perform the multiplication in $t-1$ clock cycles. The general architecture is applied to the trinomials recommended by NIST (National Institute of Standards and Technology). Furthermore, a RISC-V instruction set for the proposed multiplier is implemented and validated using VeeR-EL2 on a Nexys A7 FPGA. To the best knowledge of the authors, this is the first work that integrates the multiplication based on NIST trinomials into a RISC-V SoC. Results show an improvement of several orders of magnitude in terms of latency at a cost of less than 50% more of area.

Published
2024
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16. RISC-V Galois Field ISA Extension for Non-Binary Error-Correction Codes and Classical and Post-Quantum Cryptography

Author

Kuo, Yao-Ming, Garcia-Herrero, Francisco, Ruano, Oscar, and Maestro, Juan Antonio

Abstract

Due to the recent advances in new communication standards, such as 5G New Radio and beyond 5G, and in quantum computing and communications, new requirements for integrating processors into nodes have appeared. These requirements are meant to provide flexibility in the network to reduce operational costs and support diversity in services and load balancing. They are also designed to integrate both new and classical algorithms into efficient and universal platforms, execute specific operations, and attend to tasks with lower latency. Furthermore, some cryptographic algorithms (classical and post-quantum), which are essential to portable devices, share the same arithmetic with error-correction codes. For example, Advanced Encryption Standard (AES), elliptic curve cryptography, Classic McEliece, Hamming Quasi-Cyclic, and Reed-Solomon codes use $GF(2^{m})$GF(2m) arithmetic. As this arithmetic is the basis of many algorithms, a versatile RISC-V Galois field ISA extension is proposed in this work. The RISC-V instruction set extension is implemented and validated using SweRV-EL2 1.3 on a Nexys A7 FPGA. In addition, a five-times acceleration is achieved for AES, Reed-Solomon codes, and Classic McEliece (post-quantum cryptography) at the expense of increasing the logic utilization by 1.27%.

Published
2023
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18. ACME-2: Improving the Extraction of Essential Bits in Xilinx SRAM-Based FPGAs.

Author

Aranda, Luis Alberto, Ruano, Oscar, Garcia-Herrero, Francisco, and Maestro, Juan Antonio

Abstract

Fault emulation in field-programmable gate arrays (FPGAs) is a popular alternative to test the reliability of a design due to its low cost and high availability compared to traditional radiation-based approaches. Fault emulation is an instrumentation method based on inducing artificial bit flips on the design under test (DUT) to modify the content of its memory elements or the structure of the design itself. A major limitation of error emulation in FPGAs lies in the determination of the proper bits to test, which is directly related to the reliability results obtained and the execution times of the fault injection campaign. The Automatic Configuration Memory Error-injection (ACME) tool helps with this process in Xilinx FPGAs by obtaining the essential bits of an FPGA region where the DUT is. In this brief, we present ACME-2, an improved version of the tool where the translation from the FPGA region to design essential bits has been modified with architectural information of the FPGA. In this revision of the tool, redundant input/output routing bits that distort the reliability results are minimized. For the example designs used in the experiments, these modifications have led to an improvement in the precision of the reliability results as well as a reduction of the fault injection campaign runtime over the previous version of the tool. [ABSTRACT FROM AUTHOR]

Published
2022
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43. Design of A Parallel Decoding Method for LDPC Code Generated via Primitive Polynomial.

Author

Zhang, Zhe, Zhou, Liang, Zhou, Zhi Heng, and Garcia-Herrero, Francisco

Subjects
LOW density parity check codes, PARITY-check matrix, BIT error rate, TANNER graphs, POLYNOMIALS, MATHEMATICAL sequences
Abstract

An effective way of improving decoding performance of an LDPC code is to extend the single-decoder decoding method to a parallel decoding method with multiple sub-decoders. To this end, this paper proposes a parallel decoding method for the LDPC codes constructed by m-sequence. In this method, the sub-decoders have two types. The first one contains only one decoding module using the original parity-check constraints to implement a belief propagation (BP) algorithm. The second one consists of a pre-decode module and a decoding module. The parity-check matrices for pre-decode modules are generated by the parity-check constraints of the sub-sequences sampled from an m-sequence. Then, the number of iterations of the BP process in each pre-decode module is set as half of the girth of the parity-check matrix, resulting in the elimination of the impact of short cycles. Using maximum a posterior (MAP), the least metric selector (LMS) finally picks out a codeword from the outputs of sub-decoders. Our simulation results show that the performance gain of the proposed parallel decoding method with five sub-decoders is about 0.4 dB, compared to the single-decoder decoding method at the bit error rate (BER) of 10 − 5 . [ABSTRACT FROM AUTHOR]

Published
2021
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44. Serial Symbol-Reliability Based Algorithm for Decoding Non-Binary LDPC Codes.

Author

Garcia-Herrero, Francisco, Canet, Maria Jose, Valls, Javier, and Flanagan, Mark F.

Abstract

A symbol-reliability based decoding algorithm with serial schedule for non-binary low-density parity-check (LDPC) codes is presented. Performance results, together with implementation complexity analysis, are provided for different sample codes. The proposed algorithm achieves a similar gain to the min-max algorithm for codes with column weight dv ≥ 6, with lower complexity than previous symbol-reliability based algorithms. [ABSTRACT FROM PUBLISHER]

Published
2012
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