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The computation of the domination-type parameters is a challenging problem in Cartesian product graphs. We present an algorithmic method to compute the 2-domination number of the Cartesian product of a path with small order and any cycle, involving the (min , +) matrix product. We establish some theoretical results that provide the algorithms necessary to compute that parameter, and the main challenge to run such algorithms comes from the large size of the matrices used, which makes it necessary to improve the techniques to handle these objects. We analyze the performance of the algorithms on modern multicore CPUs and on GPUs and we show the advantages over the sequential implementation. The use of these platforms allows us to compute the 2-domination number of cylinders such that their paths have at most 12 vertices. [ABSTRACT FROM AUTHOR]

Domination-type parameters are difficult to manage in Cartesian product graphs and there is usually no general relationship between the parameter in both factors and in the product graph. This is the situation of the domination number, the Roman domination number or the 2-domination number, among others. Contrary to what happens with the domination number and the Roman domination number, the 2-domination number remains unknown in cylinders, that is, the Cartesian product of a cycle and a path and in this paper, we will compute this parameter in the cylinders with small cycles. We will develop two algorithms involving the (min, +) matrix product that will allow us to compute the desired values of γ2(Cn□Pm), with 3 ≤ n ≤ 15 and m ≤ 2. We will also pose a conjecture about the general formula for the 2-domination number in this graph class. [ABSTRACT FROM AUTHOR]

Quantum comparators hold substantial significance in the scientific community as fundamental components in a wide array of algorithms. In this research, we present an innovative approach where we explore the realm of comparator circuits, specifically focussing on three distinct circuit designs present in the literature. These circuits are notable for their use of T-gates, which have gained significant attention in circuit design due to their ability to enable the utilisation of error-correcting codes. However, it is important to note that T-gates come at a considerable computational cost. One of the key contributions of our work is the optimisation of the quantum gates used within these circuits. We articulate the proposed circuits employing Clifford+T gates, facilitating error correction code implementation. Additionally, we minimise T-gate usage, thereby reducing computational costs and fortifying circuit robustness against errors and environmental disturbances-essential for mitigating the effects of internal and external noise. Our methodology employs a bottom-up examination of comparator circuits, initiating with a detailed study of their gates. Subsequently, we systematically dissect the functions of these gates, thereby advancing towards a comprehensive understanding of the circuit's overall functionality. This meticulous examination forms the foundation of our research, enabling us to identify areas where optimisations can be made to improve their performance. [ABSTRACT FROM AUTHOR]

Electron tomography (ET) is an important technique in biosciences that is providing new insights into the cellular ultrastructure. Iterative reconstruction methods have been shown to be robust against the noise and limited-tilt range conditions present in ET. Nevertheless, these methods are not extensively used due to their computational demands. Instead, the simpler method weighted backprojection (WBP) remains prevalent. Recently, we have demonstrated that a matrix approach to WBP allows a significant reduction in processing time both on central processing units and on graphics processing units (GPUs). In this work, we extend that matrix approach to one of the most common iterative methods in ET, simultaneous iterative reconstruction technique (SIRT). We show that it is possible to implement this method targeted at GPU directly, using sparse algebra. We also analyse this approach on different GPU platforms and confirm that these implementations exhibit high performance. This may thus help to the widespread use of SIRT. [ABSTRACT FROM AUTHOR]

The so-called Hamming distance measures the difference between two binary strings A and B. In simplified form, it measures the number of changes in A to get B. This type of distance is very useful in classical computing in applications such as error correction. It is also advantageous in quantum computing, being for example widely used in quantum machine learning. Since current quantum computers have limited resources, this type of distance is particularly attractive because it can be computed using fewer qubits and operations than other distances such as Euclidean or Manhattan distances. In this paper, two circuits for calculating Hamming distances using exclusively Clifford+T gates are presented. The aim of both circuits is to reduce the quantum cost and number of T gates needed to compute the Hamming distance. The T gate is more expensive than the other gates, so this reduction will have a significant impact on the total cost of the circuits. Furthermore, the proposed circuits are implemented using only Clifford+T gates. The circuits implemented exclusively with this group of gates are compatible with proven error detection and correction codes. [ABSTRACT FROM AUTHOR]

Current quantum computers have a limited number of resources and are heavily affected by internal and external noise. Therefore, small, noise-tolerant circuits are of great interest. With regard to circuit size, it is especially important to reduce the number of required qubits. Concerning to fault-tolerance, circuits entirely built with Clifford+T gates allow the use of error correction codes. However, the T-gate has an excessive cost, so circuits with a high number of T-gates should be avoided. This work focuses on optimising in such terms an operation that is widely used in larger circuits and algorithms: the calculation of the absolute-value of two's complement encoded integers. The proposed circuit halves the number of required T gates with respect to the best circuit currently available in the literature. Moreover, our circuit requires at least 2 qubits less than the other circuits for such an operation. [ABSTRACT FROM AUTHOR]

The intrinsic high parallelism and entanglement characteristics of quantum computing have made quantum image processing techniques a focus of great interest. One of the most widely used techniques in image processing is segmentation, which in one of their most basic forms can be carried out using thresholding algorithms. In this paper, a fault-tolerant quantum dual-threshold algorithm has been proposed. This algorithm has been built using only Clifford+T gates for compatibility with error detection and correction codes. Because fault-tolerant implementation of T gates has a much higher cost than other quantum gates, our focus has been on reducing the number of these gates. This has allowed adding noise tolerance, computational cost reduction, and fault tolerance to the state-of-the-art dual-threshold segmentation circuits. Since the dual-threshold image segmentation involves the comparison operation, as part of this work we have implemented two full comparator circuits. These circuits optimize the metrics T-count and T-depth with respect to the best circuit comparators currently available in the literature. [ABSTRACT FROM AUTHOR]

The algorithms that best demonstrate the potential of quantum computing are Shor's algorithm and Grover's algorithm. To this day, new evidence continues to emerge in the form of algorithms or ingenious applications that increase the field of application of this type of computing. However, given the limited number of qubits in current quantum computers, and also the noise problems they currently suffer from, implementing optimized circuits that allow us to take full advantage of the available resources, as well as detecting and correcting the errors caused by this noise, is a priority. In this work we present several leading zero detector circuits for quantum computers and simulators, optimized in terms of noise tolerance and number of qubits. These circuits are a fundamental part in major circuits that perform operations as important and basic in computation as addition and division. [ABSTRACT FROM AUTHOR]

Abstract: A wide range of applications in engineering and scientific computing are involved in the acceleration of the sparse matrix vector product (SpMV). Graphics Processing Units (GPUs) have recently emerged as platforms that yield outstanding acceleration factors. SpMV implementations for GPUs have already appeared on the scene. This work is focused on the ELLR-T algorithm to compute SpMV on GPU architecture, its performance is strongly dependent on the optimum selection of two parameters. Therefore, taking account that the memory operations dominate the performance of ELLR-T, an analytical model is proposed in order to obtain the auto-tuning of ELLR-T for particular combinations of sparse matrix and GPU architecture. The evaluation results with a representative set of test matrices show that the average performance achieved by auto-tuned ELLR-T by means of the proposed model is near to the optimum. A comparative analysis of ELLR-T against a variety of previous proposals shows that ELLR-T with the estimated configuration reaches the best performance on GPU architecture for the representative set of test matrices. [Copyright &y& Elsevier]

This paper presents an initiative to teach computer representation of numbers and arithmetic in undergraduate courses in computer science and engineering. The approach is based upon carefully designed practical exercises that highlight the main properties and computational issues of finite-length number representation and arithmetic. In conjunction with the exercises, an auxiliary computer-based environment constitutes a valuable support tool for students to learn and understand the concepts involved. For integer representation, this work has focused on the standard 2's complement. Special emphasis has been put on the algorithms for integer arithmetic operations. For floating-point representation, simpler formats have been used as an introduction to the IEEE Standard 754, with the aim of presenting the fundamentals of the floating-point computation and emphasizing its limitations. This approach could be included in introductory courses related to computer organization, programming, discrete mathematics, or numerical methods. [ABSTRACT FROM AUTHOR]

Sparse matrix matrix (SpMM) multiplication is involved in a wide range of scientific and technical applications. The computational requirements for this kind of operation are enormous, especially for large matrices. This paper analyzes and evaluates a method to efficiently compute the SpMM product in a computing environment that includes graphics processing units (GPUs). Some libraries to compute this matricial operation can be found in the literature. However, our strategy (FastSpMM) outperforms the existing approaches because it combines the use of the ELLPACK-R storage format with the exploitation of the high ratio computation/memory access of the SpMM operation and the overlapping of CPU–GPU communications/computations by Compute Unified Device Architecture streaming computation. In this work, FastSpMM is described and its performance evaluated with regard to the CUSPARSE library (supplied by NVIDIA), which also includes routines to compute SpMM on GPUs. Experimental evaluations based on a representative set of test matrices show that, in terms of performance, FastSpMM outperforms the CUSPARSE routine as well as the implementation of the SpMM as a set of sparse matrix vector products. [ABSTRACT FROM AUTHOR]