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This article reports a 320-GHz low-jitter and low-reference-spur signal source consisting of an 80-GHz integer-N phase-locked loop (PLL) and a 320-GHz frequency quadrupler. The 80-GHz PLL features a novel dual-path quadrature exclusive-OR (QXOR) technique to cancel the spurs at the reference frequency and its harmonics, enabling low-spur and low-noise phase locking. The proposed phase detector (PD) also enables frequency detection and lock detection (LD), rendering the band-searching to be decoupled from the loop components. Implemented in a 0.13-μm SiGe BiCMOS technology, the proposed signal source shows a -73.1-dBc reference spur, -113.7-dB/Hz phase noise at 1-MHz offset at 40.96 GHz, and -90.3-dB/Hz phase noise at 1-MHz offset at 311.8 GHz. It achieves an integrated jitter of 66.9 fs $_{{rms}}$ at 40.96 GHz and 122 fs $_{{rms}}$ (both integrated from 10 kHz to 100 MHz) beyond 300 GHz, with a total division ratio of 512. The LD time is at the microsecond level. The maximum output power is -3.24 dBm, and the power consumption is 372 mW. Ministry of Education (MOE) Submitted/Accepted version This work was supported in part by the Singapore Ministry of Education Academic Research Fund Tier 2 under Grant MOE2019-T2-1-114; and in part by the Science and Technology Development Fund, Macau SAR, under Grant SKL-AMSV(UM)- 2020-2022.

This paper describes a low-power multiband blocker-tolerant receiver (RX) with three steps of filtering among two transconductance (Gm) stages. To consistently achieve low noise figure (NF) and high linearity over a wide range of operating frequency, a single-Gm low-noise amplifier (LNA) heads the RX with embedded N-path filtering, and feed-forward out-of-band (OB) blocker cancellation to surmount the tradeoff between the passband bandwidth (BW) and OB rejection without sacrificing the power budget. A filtering-by-aliasing (FA) block embeds another single-Gm baseband (BB) amplifier to allow a steep roll-off lowpass response with a clock-rate-defined passband BW. Prototyped in 28-nm CMOS, the RX achieves a 3.1-dB NF and a 5.4-dBm OB-IIP3 at 2 GHz, while consuming only 22 mW, measured at a gain of 22 dB. The tunable passband BW is 2.5 to 20 MHz, and the RF-to-BB composite filtering slope is 20 to 50 dB/10 MHz at 1.75xBW offset. The RX occupies a 0.24 mm² active area.

This paper describes a wideband ultra-fast-settling fractional-N bang-bang digital phase-locked loop (DPLL) for multi-ISM-band ultra-low-power (ULP) radios. We propose a mismatch-free digital-to-time-converter (DTC) gain calibration scheme to effectively shorten the calibration time, while the split coarse-fine PLL loops with different loop bandwidths accelerate the loop settling speed. The employed ring VCO (RVCO) aids to extend the frequency tuning range and generate multi-phase outputs. Prototyped in 65-nm CMOS, the DPLL consumes 1.2–2.4 mW over a wide frequency locking range of 68.3% (1.3–2.65 GHz) and occupies a die area of 0.12 mm2. The settling time measures $8~\mu \text{s}$ at an 82-MHz initial frequency error.

This paper proposes a surface-acoustic wave (SAW)-less tunable RF front end (RF-FE) using an electrical-balance duplexer (EBD) integrated with a switched-LC N-path low-noise amplifier (LNA). The EBD cancels the transmitter–receiver (TX–RX) leakage at the RX frequency by dynamically optimizing the balance of a hybrid transformer, which enables in-band full-duplex (IBFD) operation. A transconductor-based LNA in parallel with a switched-LC N-path network creates input and output notches to reject TX leakage for frequency-division duplexing (FDD) operation. The LNA’s signal-handling capability is enhanced via optimum switch biasing. Fabricated in 0.18- $\mu \text{m}$ SOI CMOS, the RF-FE offers >50-dB tunable rejection from the TX port to LNA output at both TX and RX frequencies, for all 3GPP bands from 0.7 to 1 GHz (i.e., FDD case). It is the first tunable RF-FE including an LNA that achieves +70-dBm TX-path IIP3, and +30-dBm in-band TX power while cancelling the self-interference by >50 dB (i.e., IBFD case). The RF-FE consumes 62.5 mW at 1 GHz with 11.7-dB RX cascaded NF, 3.6-dB TX insertion loss, and 9.62 mm2 active area.

An N-path switched-capacitor (SC) gain loop is proposed as an area-efficient surface acoustic wave-less wireless transceiver (TXR) for multiband TDD communications. Unlike the direct-conversion transmitter (TX: baseband (BB) filter $\to$ I/Q modulation $\to$ PA driver) and receiver (RX: LNA $\to$ I/Q demodulation $\to$ BB Filter) that the functions are arranged in an open-loop style, here the signal amplification, bandpass filtering, and I/Q (de)modulation are unified in a closed-loop formation, being reconfigurable as a TX or RX with a local oscillator (LO)-defined center frequency. The key advantages are the multiband operation capability in the TX mode, and high resilience to out-of-band (OB) blockers in the RX mode. Fabricated in a 65-nm CMOS, the TXR prototype consumes up to 38.4 mW (20 mW) in the TX (RX) mode at the 1.88-GHz long-term evolution (LTE)-band2. The LO-defined center frequency covers >80% of the TDD-LTE bands with neither on-chip inductors nor external input-matching components. By properly injecting (extracting) the signals into (from) the N-path SC gain loop, the TX mode achieves an −1 dBm output power, a −40 dBc ACLREUTRA1, and a 2% EVM at 1.88 GHz, while showing a −154.5 dBc/Hz OB noise at 80-MHz offset. In the RX mode, a 3.2-dB noise figure and a +8 dBm OB-IIP3 are measured. The active area (0.03 mm2) of the TXR is 24 $\times$ smaller than the state-of-the-art LTE solutions.

This paper proposes a self-interference-resilient LNA for the FDD-LTE covering 0.7 to 1GHz. It incorporates a switched-LC N-path network with gain-boosting and optimum-biasing techniques to enhance the out-of-band (OOB) linearity at ≥40MHz offset. Implemented in 0.18µm SOI CMOS, the LNA achieves >31.2dB output rejection, +26.2dBm (+8dBm) OOB-IIP3 (iB 1dB ) at ≥40MHz offset and 6.8dB blocker NF at +4dBm blocker power for the default mode, while consuming a reasonable power of 48.4 to 62.5mW. When reconfigured to high-rejection mode, the LNA offers a tunable cancellation notch improving the output rejection to >50dBc.

This paper proposes a wideband multi-stage inverter-based driver amplifier (DA) suitable for IEEE 802.22 wireless regional area network (WRAN) transmitters. In order to optimize the voltage gain, power, linearity and load drivability, the DA employs two cascaded inverters followed by a source follower, in which the second inverter employs resistive feedback and an inverter-based active load to achieve linearization. Simulated in 65 nm CMOS, the achieved voltage gain is 17.6 dB and the power is 14.6 mW at 1.2 V. The -3 dB bandwidth is 5.6 MHz to 2.17 GHz. For a 3rd-order intermodulation distortion (IMD3) of -45 dBc, the output power reaches -7.3 dBm.