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The evolution of the electrical properties of HfO2/SiO2/Si dielectric stacks under electrical stress has been investigated using atomic force microscope-based techniques. The current through the grain boundaries (GBs), which is found to be higher than thorough the grains, is correlated to a higher density of positively charged defects at the GBs. Electrical stress produces different degradation kinetics in the grains and GBs, with a much shorter time to breakdown in the latter, indicating that GBs facilitate dielectric breakdown in high-k gate stacks.

High-mobility alternative channel materials to silicon are critical to the continued scaling of MOS devices. The analysis of capacitance–voltage (C–V) measurements on these new materials with high-k gate dielectrics is a critical technique to determine many important gate-stack parameters. While there are very useful C–V analysis tools available to the community, these tools are all limited in their applicability to alternative semiconductor channel MOS gate-stack analysis since they were developed for silicon. Here, we report on a new comprehensive C–V simulation and extraction tool, called CV Alternative Channel Extraction (ACE), that incorporates a wide range of semiconductors and dielectrics with the capability to implement customized gate stacks. Fermi–Dirac carrier statistics, nonparabolic bands, and quantum mechanical effects are all implemented with options to turn each of these off as the user desires. Interface state capacitance ( ${C}_{\mathsf {it}}$ ) is implemented using a common model for systems like Si and Ge. A more complex ${C}_{\mathsf {it}}$ model is also implemented for III–Vs that accurately captures frequency dispersion in accumulation that arises from tunneling. CV ACE enables extremely fast simulation and extraction and can accommodate measurements performed at variable temperatures and frequencies to allow for a more accurate extraction of interface state density ( ${D}_{\mathsf {it}}$ ).

We propose a model describing the operations of hafnium oxide-based resistive random access memory (RRAM) devices at the microscopic level. Charge carrier and ion transport are self-consistently described starting from the leakage current in pristine HfO2. Material structural modifications occurring during the RRAM operations, such as conductive filament (CF) creation and disruption, are accounted for. The model describes the complex processes leading to a formation of the CF and its dependence on both electrical conditions (e.g., current compliance, voltage stress, and temperature) and device characteristics (e.g., electrodes material and dielectric thickness).

The total ionizing dose (TID) response of double-gate SiGe- SiO 2 /HfO 2 pMOS FinFET devices is investigated under different device bias conditions. Negative bias irradiation leads to the worst-case degradation due to increased hole trapping in the HfO 2 layer, in contrast to what is typically observed for devices with SiO 2 or HfO 2 gate dielectrics. This occurs in the devices because radiation-induced holes that are generated in the SiO 2 interfacial layer can transport and become trapped in the HfO 2 under negative bias, leading to a more negative threshold voltage shift than observed at 0 V bias. Similarly, radiation-induced electrons that are generated in the SiO 2 interfacial layer can transport into the HfO 2 and become trapped under positive bias, leading to a more positive threshold voltage shift than observed at 0 V bias.

Accurate reliability predictions of real-world digital logic circuits rely heavily on the relevancy of device-level testing. In the case of bias temperature instability (BTI), where recovery plays a significant role, a leap of faith is taken to translate device-level reliability data into a practical information for the real-world circuit implications. In this paper, we develop a methodology to bridge this gap by employing an eye diagram approach, which allows us to monitor, at circuit speed, device-level random jitter degradation in response to stress. By employing a variety of positive BTI gate voltage stress and sense bit sequences (including dc, ring oscillator (RO), and pseudorandom), we are able to compare the effectiveness of these approaches at capturing random timing jitter. We find that conventional RO-type measurements are unable to capture the random jitter degradation. This calls into question the effectiveness of using RO structures as a proxy for real-random logic circuits. Only when a pseudorandom bit sequence is employed does the true extent of jitter degradation become observable. This is an important development and serves as an accurate means to translate device-level reliability data to predict real-world digital logic circuit degradation.

A new generation of non-volatile memories that store information in a metal/insulator/metal cell with switchable electrical resistance is gaining attention due to its simple structure and high yield. Despite extensive device level measurements have been performed, the origin of the resistive switching remains unclear. In this work, we use a disruptive approach to characterize cyclic resistivity changes at the nanoscale, combining a standard conductive atomic force microscope and a semiconductor parameter analyzer. Using this setup, we are able to assess the origin of resistive switching in Hafnium-based oxides, which takes place at the grain boundaries of polycrystalline stacks, and further calculations corroborate the local nature of this phenomenon.

This paper presents a physics-based compact model for the program window in HfOx resistive random access memory devices, defined as the ratio of the resistances in high resistance state (HRS) and low resistance state (LRS). This model allows extracting the characteristics of the conductive filament (CF) in HRS. For a given forming current compliance limit, the program window is shown to be correlated to the thickness of the reoxidized portion of the CF in HRS, which can be modulated by the reset voltage amplitude. On the other hand, the statistical distribution of the memory window depends exponentially on the barrier thickness variations that points to the critical role of reset conditions for the performance optimization of RRAM devices.

We propose a physical model for the fast component ( \( s) of the positive bias temperature instability (PBTI) process in SiO x /HfO2 gate-stacks. The model is based on the electron-phonon interaction governing the trapping/emission of injected electrons at the preexisting defects in the dielectric stack. The model successfully reproduces the experimental time dependences of the \(V_{\mathrm {{TH}}}\) shift on both stress voltage and temperature. Simulations allow the extraction of the physical characteristics of the defects contributing to PBTI, which are found to match those assisting the leakage current in these stacks (i.e., oxygen vacancies).

InGaAs MOS C-V and G-V characteristics are measured under illumination to identify regions of strong minority carrier response related to surface inversion. For the MOS structure with n-type substrate biased in inversion, a high density of surface states in the proximity of the valence band edge is present that masks the response of light generated minority carriers at room temperature. Much stronger effect of illumination is observed at low temperature where the surface-state response is suppressed due to carrier freeze out. On the other hand, for the MOS structure with p-type substrate, strong minority carrier response under illumination is readily observed in inversion even at room temperature, reflecting that the density of surface states near the edge of conduction band is negligible. All the data can be explained in the framework of small-signal equivalent circuit, by modeling the minority carrier generation with a light-dependent conductance plugged in between the conduction band and the valence band. The model is validated against the measured MOS conductance with and without light in inversion.

Variability in resistive switching memory (RRAM) devices is studied by applying an AC measurement setup capable of efficiently collecting read current data in low and high resistance states (LRS and HRS, respectively) in each consecutive pulse SET/RESET cycle. It is found that HRS and LRS read current values follow the lognormal and normal distributions, respectively. Endurance test demonstrates that, in a small percentage of cycles, the set operation may fail, which might be missed when a conventional approach of a limited number of read operations is employed.

Instability of InGaAs channel nMOSFETs with the Al2O3/ ZrO2 gate stack under positive bias stress demonstrates recoverable and unrecoverable components, which can be tentatively assigned to the pre-existing and generated defects, respectively. The recoverable component is determined to be primarily associated with the defects in the Al2O3 interfacial layer (IL), the slow trapping at which is responsible for the power law time dependency of the threshold voltage shift and transconductance change. The fast electron trapping in the ZrO2 film exhibits negligible recovery, in contrast to the Si-based devices with a similar high-k dielectric film. Generation of new electron trapping defects is found to occur in the IL, preferentially in the region close to the substrate, while trap generation in the high-k dielectric is negligible.

BeO was investigated as the interface passivation layer (IPL) between a high-k dielectric and a III-V compound semiconductor substrate in metal-oxide-semiconductor (MOS) devices. One of the critical issues facing the fabrication of next generation MOS devices is the minimization of damage to the III-V semiconductor substrate during the etching of the thin IPL. In this study, atomic layer etching (ALET) was investigated for etching of BeO as the IPL on a GaAs substrate to control the etch depth precisely and to minimize the damage to the III-V semiconductor substrate. By using ALET to etch BeO, which uses BCl"3 as the adsorption gas for the formation of chloride compounds (Be-Cl and BCl-O) and Ar as the desorption gas for the removal of the chloride compounds, a self-limited, one-monolayer etch rate of about 0.75A/cycle was achieved with no increase of surface roughness and without change of surface composition. Moreover, under the BeO ALET conditions, which are able to precisely stop etching over the GaAs substrate after removing BeO, the exposed GaAs substrate showed surface composition and surface roughness similar to those of the as-received GaAs substrate.

We report on the investigation of the charge trapping characteristics of dielectric-gated AlGaN/GaN high electron mobility transistors (HEMTs) with atomic layer deposited HfO2 (Tetrakis-(ethylmethylamino)hafnium and H2O precursors). The impact of process development and tool contamination in an Au-free 200-mm silicon CMOS line is discussed. The interfacial GaOxNy layer is proposed to be the primary location of long time constant traps. We examine the impact of these trap states on threshold voltage engineering of the gate stack. Enhancement mode operation of HEMTs is demonstrated, and the stability of enhancement mode is discussed.

Graphical abstractDisplay Omitted The origin of the TDDB bimodality was studied in high-k (HK) gate stacks using a CAFM.The roles of the interfacial layer/HK layer and the HfO2 polycrystalline structure were evaluated.Bimodal characteristic was attributed to the different electrical properties of Gs and GBs.BD preferentially occurs in the interfacial SiO2 (IL) layer beneath the GBs.The gate stack BD is triggered by the BD of the SiO2 layer. Dielectric breakdown (BD) in polycrystalline HfO2/SiO2 gate stacks has been studied using a conductive atomic force microscopy (CAFM) technique, which allows employing a nanosize probe to apply a highly localized electrical stress. The resulting BD statistics indicate that BD preferentially occurs in the interfacial SiO2 (IL) layer beneath the grain boundaries (GBs) of the overlaying polycrystalline HfO2 film due to higher conductivity of the GB compared to that of the grains.

We study resistive switching memories with Hf or Ti metal oxygen exchange layers.STEM dark field and EELS are used to observe the conductive filament.The filament is a cone-shaped metal-rich region in the HfO2 dielectric layer.Composition of the metallic filament is dominated by Hf or Ti depending on the OEL. A detailed physical analysis of the conductive filament electrically formed in HfO2-based resistive switching memory devices with both Hf and Ti metal oxygen exchange layers is presented. The filament, observed by applying transmission electron microscopy (TEM), scanning TEM (STEM), and electron energy loss spectroscopy (EELS) techniques to 50i?50nm2 cells, is a cone-shaped metal-rich region in the HfO2 dielectric of the resistive switching device.

For the metal gate patterning of metal gate/high-k dielectric complementary metal–oxide–semiconductor field effect transistors (CMOSFETs), plasma induced damage (PID) was identified during the etching by a conventional reactive ion etching (RIE) and, a neutral beam etching (NBE) technique. NBE uses reactive radical beam instead of reactive ions for RIE. Improved device characteristics such as the mobility, the transconductance, subthreshold slope, and drain current could be observed. Particularly, the application of the NBE to PMOSFET was more effective than that to NMOSFET. This improvement was related to the decreased interface trap density at the gate dielectric of CMOSFEETs.

In this paper we analyze Random Telegraph Signal (RTS) noise and Power Spectral Density (PSD) in hafnium-based RRAMs. RTS measured in HRS exhibits fast and slow multilevel switching events. RTS characteristics are examined through novel color-coded time-lag plots and Hidden Markov Model (HMM) time-series analyses. Results are validated by comparing simulated and experimental PSD. Noise is examined at different reset conditions to provide an insight into the conduction mechanisms in HRS. Higher reset voltages are found to result in greater RTS complexity due to a larger number of active traps as confirmed by PSD.

We introduce a data analysis methodology for multifrequency charge-pumping (CP) measurements, which allows extracting both spatial and energy profiles of the CP-active traps in the gate dielectrics along with the defect energy characteristics. The analysis is based on the charge trapping/detrapping model accounting for carriers tunneling between the substrate and the oxide traps and multiphonon-assisted structural trap relaxation associated with charge carrier localization in the trap. Comparison of the spatial and energy trap distribution profiles obtained from CP data collected on a set of high-k dielectric gate stacks of different thicknesses facilitate the calibration of the model parameters. Extraction of the bulk trap characteristics, including trap ionization and relaxation energies, extends the utility of the CP technique from quantifying defect density toward identifying the nature of defects in the dielectric.

Spike-timing-dependent plasticity (STDP) is a fundamental learning rule observed in biological synapses that is desirable to replicate in neuromorphic electronic systems. Nanocrystalline-silicon thin film transistors (TFTs) and memristors can be fabricated at low temperatures, and are suitable for use in such systems because of their potential for high density, 3-D integration. In this paper, a compact and robust learning circuit that implements STDP using biologically realistic nonmodulated rectangular voltage pulses is demonstrated. This is accomplished through the use of a novel nanoparticle memory-TFT with short retention time at the output of the neuron circuit that drives memristive synapses. Similarities to biological measurements are examined with single and repeating spike pairs or different timing intervals and frequencies, as well as with spike triplets.

Atomic layer etching (ALE) has been applied to the high-k dielectric patterning in complementary metal–oxide–semiconductor field effect transistors (CMOSFETs), and its electrical characteristics were compared with those etched by conventional etching such as wet etching (WE) or reactive ion etching (RIE). The CMOSFET etched by the ALE showed the improvement of the off-state leakage current (Ioff), which was mainly attributed to the decreased perimeter component of the gate leakage current (IG) particularly, at the low field region. The better electrical characteristics are due to the low trap density at the edge of gate oxides in the S/D region of CMOSFETs.

Capacitance-voltage ( $C$ – $V$ ) measurement and analysis is highly useful for determining important information about MOS gate stacks. Parameters such as the equivalent oxide thickness (EOT), substrate doping density, flatband voltage, fixed oxide charge, density of interface traps ( ${D}_{ \rm {it}}$ ), and effective gate work function can all be extracted from experimental $C$ – $V$ curves. However, to extract these gate-stack parameters accurately, the correct models must be utilized. In Part I, we described the modeling and implementation of a $C$ – $V$ code that can be used for alternative channel semiconductors in conjunction with high- $k$ gate dielectrics and metal gates. Importantly, this new code (CV ACE) includes the effects of nonparabolic bands and quantum capacitance, enabling accurate models to be applied to experimental $C$ – $V$ curves. In this paper, we demonstrate the capabilities of this new code to extract accurate parameters, including EOT and ${D}_{ \rm {it}}$ profiles from experimental high- $k$ on Ge and In0.53Ga0.47As gate stacks.

The accuracy of the split-CV mobility extraction method is analyzed in buried-channel InGaAs MOSFETs with a Al2O3 gate dielectric and an InP barrier, through a “simulated experiment” procedure using 2-D numerical device simulations that are preliminarily calibrated against experimental I-V and CV curves. The different error sources limiting the method accuracy are pointed out. It is suggested that, as a result of these errors, the split- CV method can appreciably underestimate the actual channel mobility in these devices, with an error of >;20% and >;50% on peak mobility and high-VGS mobility, respectively. The method should therefore not be adopted for accurate mobility measurement in this operating regime but only as a fast response technique providing a conservative estimation of channel mobility. Moreover, the method provides mobility values that rapidly drop below the peak value for decreasing VGS. It is shown that this behavior can be an artifact of the extraction method, which may mask physical mechanisms causing a real mobility drop with decreasing channel carrier density, such as Coulomb scattering mechanisms. This poses limitations to the adoption of split-CV mobility as a reference for mobility model assessment in this operating regime. The proposed methodology can be applied to other III-V FETs, including both heterostructure-based and inversion-mode devices.

The information on the subtle local structural modifications around the Hf atom in HfO2 high-k dielectric stacks has been demonstrated to be crucial in determining the resulting electronic properties of the complementary metal oxide (CMOS) devices. In this work, using extended X-ray-absorption fine structure (EXAFS) spectroscopy, the local structural characterization of Hf-based advanced gate stacks thin films were investigated. The thin film stacks used in this project are Al2O3 capped HfO2 thin films deposited on silicon substrates. EXAFS simulations and fits were applied to the data in order to extract crucial structural modifications on these films upon postdeposition annealing (PDA). The local crystal symmetry and coordination around the Hf atom were investigated under various annealing conditions. Specifically, in Hf-based dielectric thin films on silicon substrates capped with Al2O3 layers, the local crystal symmetry, and coordination around the Hf atom were investigated under various annealing conditions. The questions addressed are the effects of various annealing mechanisms to the diffusion mechanisms in the cap layers and modifications on the emerging local structures around the Hf atom. The diffusion of Al into HfO2 films were monitored through the EXAFS simulations. The non-linear least-squares fitting to the EXAFS data revealed that the PDA in NH3 (or N2) ambient after HfO2 deposition had prevented Al diffusion to the HfO2 layers.