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Actually, application fields, such as medicine, space exploration, surveillance, authentication, HDTV, and automated industry inspection, require capturing, storing and processing continuous streams of video data. Consequently, different process techniques (video enhancement, segmentation, object detection, or video compression, as examples) are involved in these applications. Such techniques often require a significant number of operations depending on the algorithm complexity and the video resolution, which make impossible a time efficient software implementation. The actual demand, driven by the consumer electronics market, of lightweight and high performance portable systems capable of processing high definition (HD) video sequences in real-time is therefore mainly targeted through the use of integrated digital electronic systems. Very high performance can be obtained by using full custom ASIC implementations. However, the complexity and the cost associated with ASIC design is significant. Moreover, ASIC implementations are not reconfigurable and require a long design time. For these reasons, Field Programmable Gate Array (FPGA) devices are more and more being chosen as target technology for the hardware acceleration. In this dissertation, several hardware architectures for real-time video processing of HD video sequences are proposed. The circuits are designed by using Hardware Description Languages (HDL) and the target technologies for the implementation are mainly FPGA devices. Area utilization, maximum working frequency, and power dissipation are also computed and analyzed for all the described architectures and several experiments are carried out to test the circuits characteristics. The comparison with previously proposed works shows that circuits performance overcome the state-of-the-art architectures, highlighting the effectiveness of the proposed solutions.

The hardware computation of the logarithm function is required in several applications, ranging from signal and image processing to telecommunication systems. This brief shows that most of previous proposed logarithmic converters, based on piecewise linear approximations, suffer from large errors when dealing with fixed-point input values with many fractional bits, a situation often encountered in practical applications. Thus, this brief proposes a novel logarithmic converter, using nonuniform segmentation and piecewise linear approximation. A rigorous technique that allows computing the optimal segmentation and the coefficients values for a prescribed precision is described in this brief. For fixed-point input values, the proposed approach allows obtaining a sensibly lower error, for the same number of nonuniform segments, compared with previously published results. Implementation details and synthesis results in a 65-nm CMOS technology are also presented.

The Direct Digital Frequency Synthesizer (DDFS) is a critical component routinely implemented in communication or signal processing systems. The recent literature proposes various DDFS implementation techniques that, implemented by using state of the art Application Specific Integrated Circuits (ASIC) technologies, provide ever improving performances in terms of speed, power dissipation and silicon area occupation. The performance trend provided by the advanced designs that target ASIC technologies, is not guaranteed to remain the same when the target technology is a commercially available Field Programmable Gate Array (FPGA) device. This paper presents the FPGA implementation of the best performing DDFS architectures proposed to date. DDFS performance trends are compared with the ASIC implementations. Further, the state of the art DDFS circuits are modified in order to better suit the FPGA technology and compared against the DDFS implementations obtained using Intellectual Properties (IPs) included in the design suites of the FPGA manufacturers. The comparison is conducted considering as implementation target various (both low end, middle range, and high end) FPGA devices produced by different vendors. Considered performance parameters are the maximum working frequency, the dynamic power dissipation, the logic resource occupation, and the precision of the DDFS measured in terms of Spurious Free Dynamic Range (SFDR). The analysis shows that when dealing with FPGA implementations, it is important that the implemented architectures adapt to the internal logic resources of the FPGA. For low SFDR values the best performing architectures are the straightforward ROM based ones that optimally fit in the very fast Block RAM of the FPGA. When the required SFDR increases more advanced architectures are required. The optimal architectures also depend on the design choice of privileging high working frequency or reduced power dissipation.

Circuits and systems able to process high quality video in real time are fundamental in nowadays imaging systems. The circuit proposed in the paper, aimed at the robust identification of the background in video streams, implements the improved formulation of the Gaussian Mixture Model (GMM) algorithm that is included in the OpenCV library. An innovative, hardware oriented, formulation of the GMM equations, the use of truncated binary multipliers, and ROM compression techniques allow reduced hardware complexity and increased processing capability. The proposed circuit has been designed having commercial FPGA devices as target and provides speed and logic resources occupation that overcome previously proposed implementations. The circuit, when implemented on Virtex6 or StratixIV, processes more than 45 frame per second in 1080p format and uses few percent of FPGA logic resources.

Reliability and performance of electronic devices are significantly dependent on their noise rejection capability that is usually investigated since their early production stage as well as during the scheduled maintenance. To this aim, white noise sources are mostly available on the market and usually to the purpose, whereas the use of generators capable of producing coloured noise (actually, very uncommon) should be advisable in most of applications. If arbitrary waveform generators (AWGs) are taken into account, either transient signals in single shot generation mode or periodic signals in continuous generation mode can only be produced due to the finite available memory; unfortunately, both modes are not suitable to emulate noise. To overcome the considered limitations, this work presents the design and implementation of a coloured noise generator that offers the possibility of tailoring the noise spectral content to the desired application. As it can be expected, performance of the generator changes according to different hardware selections; with specific regard to the proposed implementation, it performs as good as state of art solutions in terms of both bandwidth and flexibility. It is composed of a digital section implemented on field programmable gate arrays (FPGA) and a digital-to-analogue converter (DAC) mandated to generate the desired analogue output. The bandwidth of the generated noise can be selected up to a maximum of 50 MHz while the evolution of power spectral density versus frequency can be defined with a resolution equal to 0.4% of the bandwidth. Thanks to suitable digital signal processing techniques, spurious components laying outside the selected bandwidth are hardly attenuated.

An electronic system for the real-time denoising of fluoroscopic images is proposed in this paper. Fluoroscopic devices use X-rays to obtain real-time moving images of patients and support many surgical interventions and a variety of diagnostic procedures. In order to avoid risks for the patient, X-ray intensity has to be kept acceptably low during the clinical applications. This implies that fluoroscopic images are corrupted by large quantum noise (Poisson-distributed). Real-time noise reduction can offer a better visual perception to doctors and possible further reductions of the dose. The proposed circuit implements a spatio-temporal filter optimized for the removal of the quantum noise while preserving video edges and the prompt response of the image to the introduction of new features in the field. The filter incorporates information on the dependence of the standard deviation of the noise on the local brightness of the image and performs a conditioned average operation. The proposed circuit is implemented on FPGA (Field Programmable Gate Array) device allowing the real time elaboration of video streams composed by frames with 1024×1024 pixel and uses an external DDR2 (Double Data Rate 2) memory for the storage and the reuse of the fluoroscopic frames needed by the filter. When implemented on StratixIV-GX70 FPGA the circuit is able to process up to 49 fps (frames per second) while using 80% of the logic resources of the FPGA.

Noise sources are needed for test and validation of noise sensitive electronic systems but only wide band white noise sources are directly available on the market. In this paper a programmable colored noise generator is proposed. The system allows to configure the spectral features of the noise and is implemented with a Field Programmable Gate Array that produces the digital samples of the noise and a Digital to Analog Converter that produces the analogue output. The proposed generator overcomes the state of the art in terms of bandwidth and flexibility and produces a noise sequence whose length is unlimited for practical purposes. Experimental results show that the bandwidth of the generated noise can be selected up to a maximum of 120 MHz while defining the power spectral density with a frequency resolution equal to 0.2 % of the selected bandwidth.

The processing capabilities that are included into the acquisition block of the real-time digital oscilloscopes largely contribute to determine the overall performance of the instrument. Their remarkable improvement has made it possible to enhance the performance in terms of increased measurement rate, automation, and reduced measurement uncertainty related to quantization and noise. This paper presents the implementation of a preprocessing circuit for a novel acquisition mode of bandpass signals, which is characterized by an increased vertical resolution. Although the theoretical foundations were recently presented with simulative results, here, the circuital implementation of such an acquisition mode is presented. The focus is on mid or low cost digital oscilloscopes that can improve their vertical resolution at a negligible additional cost. First, a preliminary field programmable gate array implementation is considered to evaluate the achievable performance both from a theoretical point of view and throughout experimental tests. Then, a custom application specific integrated circuit implementation, in 28-nm complementary metal-oxide-semiconductor technology is analyzed. Along with the parameter optimization, the work experimentally tests the acquisition mode and evaluates the effects of nonideal characteristics such as finite word length and nonideal filtering. The increase in the effective number of bit (ENoB) is up to 2.5 bit, whereas the ENoB degradation because of word length and nonideal filtering is quantified as ~ 1.1 and 0.5 bit. The design highlights that there is substantial margin for parallel implementation that is the base to candidate the proposed solution as a remarkable option for the next generation oscilloscopes.

Direct Digital Frequency Synthesizer (DDFS) circuits are routinely implemented in many electronic systems. Advanced DDFS design techniques have been proposed and optimized for ASIC (Application Specific Integrated Circuits) implementations. Nowadays, FPGA devices are frequently chosen as target for digital circuits. This paper presents the FPGA implementation of state of the art DDFS architectures and compares their performance providing hints on optimal design as a function of the chosen performance parameter.

The Direct Digital Frequency Synthesizer (DDFS) is a critical component routinely implemented in many electronic systems. Advanced DDFS design techniques have been proposed but they optimize the performance for a given ASIC (Application Specific Integrated Circuits) technology. Nowadays, FPGA are very often used for the release of electronic systems. As a consequence, the study of the performance of advanced DDFS design techniques when implemented on FPGA devices, is of great interest. The paper presents various implementation of state of the art DDFS on various FPGA and compares their performance providing hints on optimal design as a function of the chosen performance parameter.

The identification of moving objects is a fundamental step in computer vision processing chains. The development of low cost and lightweight smart cameras steadily increases the request of efficient and high performance circuits able to process high definition video in real time. The paper proposes two processor cores aimed to perform the real time background identification on High Definition (HD, 1920 1080 pixel) video streams. The implemented algorithm is the OpenCV version of the Gaussian Mixture Model (GMM), an high performance probabilistic algorithm for the segmentation of the background that is however computationally intensive and impossible to implement on general purpose CPU with the constraint of real time processing. In the proposed paper, the equations of the OpenCV GMM algorithm are optimized in such a way that a lightweight and low power implementation of the algorithm is obtained. The reported performances are also the result of the use of state of the art truncated binary multipliers and ROM compression techniques for the implementation of the non-linear functions. The first circuit has commercial FPGA devices as a target and provides speed and logic resource occupation that overcome previously proposed implementations. The second circuit is oriented to an ASIC (UMC-90nm) standard cell implementation. Both implementations are able to process more than 60 frames per second in 1080p format, a frame rate compatible with HD television.

The identification of moving objects is a basic step in computer vision. The identification begins with the segmentation and is followed by a denoising phase. This paper proposes the FPGA hardware implementation of segmentation and denoising unit. The segmentation is conducted using the Gaussian mixture model (GMM), a probabilistic method for the segmentation of the background. The denoising is conducted implementing the morphological operators of erosion, dilation, opening and closing. The proposed circuit is optimized to perform real time processing of HD video sequences (1,920 × 1,080 @ 20 fps) when implemented on FPGA devices. The circuit uses an optimized fixed width representation of the data and implements high performance arithmetic circuits. The circuit is implemented on Xilinx and Altera FPGA. Implemented on xc5vlx50 Virtex5 FPGA, it can process 24 fps of an HD video using 1,179 Slice LUTs and 291 Slice Registers; the dynamic power dissipation is 0.46 mW/MHz. Implemented on EP2S15F484C3 StratixII, it provides a maximum working frequency of 44.03 MHz employing 5038 Logic Elements and 7,957 flip flop with a dynamic power dissipation of 4.03 mW/MHz.

Background identification is a common feature in many video processing systems. This paper proposes two hardware implementations of the OpenCV version of the Gaussian mixture model (GMM), a background identification algorithm. The implemented version of the algorithm allows a fast initialization of the background model while an innovative, hardware-oriented, formulation of the GMM equations makes the proposed circuits able to perform real-time background identification on high definition (HD) video sequences with frame size 1920 × 1080. The first of the two circuits is designed with commercial field-programmable gate-array (FPGA) devices as target. When implemented on Virtex6 vlx75t, the proposed circuit process 91 HD fps (frames per second) and uses 3% of FPGA logic resources. The second circuit is oriented to the implementation in UMC-90 nm CMOS standard cell technology, and is proposed in two versions. Both versions can process at a frame rate higher than 60 HD fps. The first version uses the constant voltage scaling technique to provide a low power implementation. It provides silicon area occupation of 28847 μm2 and energy dissipation per pixel of 15.3 pJ/pixel. The second version is designed to reduce silicon area utilization and occupies 21847 μm2 with an energy dissipation of 49.4 pJ/pixel.

The paper proposes the hardware implementation of the Gaussian Mixture Model (GMM) algorithm included in the OpenCV library. The OpenCV GMM algorithm is adapted to allow the FPGA implementation while providing a minimal impact on the quality of the processed videos. The circuit performs 30 frame per second (fps) background (Bg) identification on High Definition (HD) video sequences when implemented on commercial FPGA and outperforms previously proposed implementations. When implemented on Virtex5 lx50 FPGA using one level of pipeline, runs at 95.3 MHz, uses 5.3% of FPGA resources with a power dissipation of 1.47 mW/MHz.

The real time detection of moving objects in video sequences has many important applications . This paper proposes the FPGA hardware implementation of segmentation and denoising units. The segmentation is conducted using the Gaussian Mixture Model (GMM), a probabilistic method for the moving objects identification. The implemented algorithm is the OpenCV (Open source Computer Vision library) version of the GMM. The denoising is conducted implementing the morphological operators of erosion, dilation, opening and closing. The proposed HW design achieves real time processing of HD (High Definition, frame size 1920x1080) video sequences.

The paper proposes an improved hardware implementation of the OpenCV version of the Gaussian Mixture Model (GMM) algorithm. Truncated binary multipliers and a ROM compression technique are employed to reduce hardware complexity while increasing circuit processing capability. The OpenCV GMM algorithm is adapted to allow the FPGA implementation while providing a minimal impact on the quality of the processed videos. When implemented on Virtex5 FPGA the proposed circuit is able to process High Definition (HD) video sequences at 30 frame per second (fps) improving the performances with respect to previously proposed implementations (-7.6% in area and +12.6% in speed).

The background identification methods are used in many fields like video surveillance and traffic monitoring. In this paper we propose a hardware implementation of the Gaussian Mixture Model algorithm able to perform background identification on HD images. The proposed circuit is based on the OpenCV implementation, particularly suited to improve the initial background learning phase. Bit-width has been optimized in order to reduce hardware complexity and increase working speed. The proposed circuit processes 22 1920×1080 frames per second when implemented on Virtex 5 FPGA.