1. Pin-3D
- Author
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Rwik Sengupta, Sung Kyu Lim, Sai Pentapati, Gerousis Vassilios, and Kyungwook Chang
- Subjects
Computer science ,business.industry ,Three-dimensional integrated circuit ,Hardware_PERFORMANCEANDRELIABILITY ,02 engineering and technology ,Timing closure ,Integrated circuit layout ,Die (integrated circuit) ,020202 computer hardware & architecture ,Logic synthesis ,Embedded system ,Logic gate ,Hardware_INTEGRATEDCIRCUITS ,0202 electrical engineering, electronic engineering, information engineering ,Node (circuits) ,Routing (electronic design automation) ,business - Abstract
In this paper, we present an optimization flow for monolithic 3D ICs called Pin-3D Optimizer. Compared with the state-of-the-art RTL-to-GDS flows that rely on ad-hoc technology file tweaks and RC scaling, Pin-3D offers a streamlined method to run commercial 2D IC tools to obtain high-quality monolithic 3D IC designs. Specifically, Pin-3D supports effective legalization, routing, timing closure, and ECO optimization for monolithic 3D IC designs. We propose a novel optimization methodology where the cells in each tier of a 3D IC are optimized using cell data and constraints of the full 3D design. The optimizations in a tier also directly influence the timing, power in the other tiers, leading to better overall PPA of the 3D IC. With the help of two industry processors designed with a 28 nm technology node, we show that Pin-3D provides up-to 9.0% smaller wirelength and 88% smaller total negative slack than die-by-die M3D flows. We also observe up-to 8.7% lower power and 26% smaller wirelength than 2D ICs. In addition, Pin-3D is the first flow that supports routing and timing optimization in heterogeneous logic-on-logic monolithic 3D ICs. We demonstrate this capability by performing area-balanced tier partitioning, routing, and timing closure of a 3D design with different technologies on each die.
- Published
- 2020