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A cost competitive 20nm technology node is described that enabled industry-first 20nm cellular modem chip with 2× peak data rates vs 28nm, and 2× carrier aggregation. Process and design enhancements for layout context optimization, and continuous process improvements resulted in 18% boost in circuit performance while simultaneously achieving >30% power reduction. 3 mask local interconnect and 64nm double patterning lower level metals - with yield-friendly single color pitch of 95nm and M1 special constructs with 90nm (=gate pitch) single color pitch for cell abutment - were used for achieving ~2× gate density. Single patterning 80nm pitch metal for routing levels was optimized for both density and performance. Active/passive device and double pattern metal mask count was optimized to reach process should-cost goals. Resulting technology provides cost reduction vs 28 HKMG per close to historical trend, and also cost-competitiveness vs 28 PolySiON. Leveraging of yield learning of this common back-end metallization results in up to 6 month pull-in of 16nm Finfet node yield ramp.

The form factor of mobile devices and their associated thermal dissipation characteristics present practical limits to SoC (and specifically CPU) power consumption. Multiple maximum temperature constraints interact with the thermal “time constant” of package and product to limit allowable die temperature. This can constrain maximum CPU frequency in real use cases. The co-design of product and process technology is required to maximize thermally constrained performance. Technology features, device Ieff/Ioff setpoints, and circuit design styles are all levers to optimize thermally constrained performance. A methodology for early prediction of product sensitivities to these levers is required to enable their definition sufficiently early in the development cycle of the technology node.