152 results on '"Goglin, Brice"'
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2. A survey of software techniques to emulate heterogeneous memory systems in high-performance computing
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Foyer, Clément, Goglin, Brice, and Rubio Proaño, Andrès
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- 2023
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3. Relative Performance Projection on Arm Architectures
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Gavoille, Clément, Taboada, Hugo, Carribault, Patrick, Dupros, Fabrice, Goglin, Brice, Jeannot, Emmanuel, Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Cano, José, editor, and Trinder, Phil, editor
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- 2022
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4. Towards EXtreme scale technologies and accelerators for euROhpc hw/Sw supercomputing applications for exascale: The TEXTAROSSA approach
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Agosta, Giovanni, Aldinucci, Marco, Alvarez, Carlos, Ammendola, Roberto, Arfat, Yasir, Beaumont, Olivier, Bernaschi, Massimo, Biagioni, Andrea, Boccali, Tommaso, Bramas, Berenger, Brandolese, Carlo, Cantalupo, Barbara, Carrozzo, Mauro, Cattaneo, Daniele, Celestini, Alessandro, Celino, Massimo, Colonnelli, Iacopo, Cretaro, Paolo, D’Ambra, Pasqua, Danelutto, Marco, Esposito, Roberto, Eyraud-Dubois, Lionel, Filgueras, Antonio, Fornaciari, William, Frezza, Ottorino, Galimberti, Andrea, Giacomini, Francesco, Goglin, Brice, Gregori, Daniele, Guermouche, Abdou, Iannone, Francesco, Kulczewski, Michal, Lo Cicero, Francesca, Lonardo, Alessandro, Martinelli, Alberto R., Martinelli, Michele, Martorell, Xavier, Massari, Giuseppe, Montangero, Simone, Mittone, Gianluca, Namyst, Raymond, Oleksiak, Ariel, Palazzari, Paolo, Paolucci, Pier Stanislao, Reghenzani, Federico, Rossi, Cristian, Saponara, Sergio, Simula, Francesco, Terraneo, Federico, Thibault, Samuel, Torquati, Massimo, Turisini, Matteo, Vicini, Piero, Vidal, Miquel, Zoni, Davide, and Zummo, Giuseppe
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- 2022
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5. Relative Performance Projection on Arm Architectures
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Gavoille, Clément, primary, Taboada, Hugo, additional, Carribault, Patrick, additional, Dupros, Fabrice, additional, Goglin, Brice, additional, and Jeannot, Emmanuel, additional
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- 2022
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6. Opportunities for Partitioning Non-volatile Memory DIMMs Between Co-scheduled Jobs on HPC Nodes
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Goglin, Brice, Rubio Proaño, Andrès, Goos, Gerhard, Founding Editor, Hartmanis, Juris, Founding Editor, Bertino, Elisa, Editorial Board Member, Gao, Wen, Editorial Board Member, Steffen, Bernhard, Editorial Board Member, Woeginger, Gerhard, Editorial Board Member, Yung, Moti, Editorial Board Member, Schwardmann, Ulrich, editor, Boehme, Christian, editor, B. Heras, Dora, editor, Cardellini, Valeria, editor, Jeannot, Emmanuel, editor, Salis, Antonio, editor, Schifanella, Claudio, editor, Manumachu, Ravi Reddy, editor, Schwamborn, Dieter, editor, Ricci, Laura, editor, Sangyoon, Oh, editor, Gruber, Thomas, editor, Antonelli, Laura, editor, and Scott, Stephen L., editor
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- 2020
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7. Netloc: A Tool for Topology-Aware Process Mapping
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Bordage, Cyril, Foyer, Clément, Goglin, Brice, Hutchison, David, Series Editor, Kanade, Takeo, Series Editor, Kittler, Josef, Series Editor, Kleinberg, Jon M., Series Editor, Mattern, Friedemann, Series Editor, Mitchell, John C., Series Editor, Naor, Moni, Series Editor, Pandu Rangan, C., Series Editor, Steffen, Bernhard, Series Editor, Terzopoulos, Demetri, Series Editor, Tygar, Doug, Series Editor, Weikum, Gerhard, Series Editor, Heras, Dora B., editor, Bougé, Luc, editor, Mencagli, Gabriele, editor, Jeannot, Emmanuel, editor, Sakellariou, Rizos, editor, Badia, Rosa M., editor, Barbosa, Jorge G., editor, Ricci, Laura, editor, Scott, Stephen L., editor, Lankes, Stefan, editor, and Weidendorfer, Josef, editor
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- 2018
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8. Modeling Large Compute Nodes with Heterogeneous Memories with Cache-Aware Roofline Model
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Denoyelle, Nicolas, Goglin, Brice, Ilic, Aleksandar, Jeannot, Emmanuel, Sousa, Leonel, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Jarvis, Stephen, editor, Wright, Steven, editor, and Hammond, Simon, editor
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- 2018
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9. Opportunities for Partitioning Non-volatile Memory DIMMs Between Co-scheduled Jobs on HPC Nodes
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Goglin, Brice, primary and Rubio Proaño, Andrès, additional
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- 2020
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10. An Efficient OpenMP Runtime System for Hierarchical Arch
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Thibault, Samuel, Broquedis, François, Goglin, Brice, Namyst, Raymond, and Wacrenier, Pierre-André
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Computer Science - Programming Languages - Abstract
Exploiting the full computational power of always deeper hierarchical multiprocessor machines requires a very careful distribution of threads and data among the underlying non-uniform architecture. The emergence of multi-core chips and NUMA machines makes it important to minimize the number of remote memory accesses, to favor cache affinities, and to guarantee fast completion of synchronization steps. By using the BubbleSched platform as a threading backend for the GOMP OpenMP compiler, we are able to easily transpose affinities of thread teams into scheduling hints using abstractions called bubbles. We then propose a scheduling strategy suited to nested OpenMP parallelism. The resulting preliminary performance evaluations show an important improvement of the speedup on a typical NAS OpenMP benchmark application.
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- 2007
11. Hardware topology management in MPI applications through hierarchical communicators
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Goglin, Brice, Jeannot, Emmanuel, Mansouri, Farouk, and Mercier, Guillaume
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- 2018
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12. D5.1 Software Specification
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Pickartz, Simon, Moschny, Thomas, Couvée, Philippe, Lemarinier, Pierre, Cedeyn, Aurélien, Agosta, Giovanni, Cattaneo, D, Fornaciari, William, Zaccaria, V, Bartolini, Andrea, Torquati , Massimo, Aldinucci, Marco, Colonnelli, Iacopo, Martinelli, A, Guimarães, V, Mohr, Bernd, Goglin, Brice, Clauss, Carsten, Krempel, Stephan, Rauh, Michael, Bartelheimer, Niklas, Neuwirth, Sarah, and Vysocký, Ondrej
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Exascale ,HPC ,EUPEX ,Software - Abstract
The modular design of the European Pilot for eXascale (EUPEX) platform has a strong impact on the architecture of the software ecosystem. The Modular Supercomputer Architecture (MSA) adds an additional level in the hierarchy of traditional supercomputing systems by introducing the concept of tightly-coupled modules. Each module, in turn, is a parallel computer1 with hardware characteristics satisfying the requirements of a specific type of application or parts thereof. The tight coupling is ensured by means of a federated high-speed network joining potentially different, module-specific fabrics. This architectural approach comes with advantages compared to traditional designs and chal-lenges regarding the whole software stack ranging from the management layer up to the appli-cation level. The notion of modules enables MSA systems to evolve over time, i. e., instead of disassembling a system after its lifetime, modules can be added and/or removed. However, this requires support of the management software providing the ability to insert or remove modules with minimal effort and impact on the system’s operation, i. e., large system downtimes have to be avoided. The execution environment has to be capable of providing an efficient access to all system resources to the applications. On the one hand, this requires the ability to execute parallel workloads transparently across multiple modules. On the other hand, it should also allow applications to leverage topological information on the MSA hierarchy for further optimisation. This requires close interaction with the runtime environment providing Application Programming Interfaces (APIs) for accessing this information. Power management, energy efficiency, and performance optimisation are crucial to achieve Exascale performance while meeting a reasonable power budget. Therefore, tools for monitoringand profiling have to be adapted to the design of the EUPEX platform covering all levels ranging from the system level, via the node level through to the application level. Finally, the I/O system is also affected by the modular system design. Instead of a single, central storage, MSA system exhibit a multi-level storage hierarchy with different characteristics. The system software faces the challenge of providing fast and scalable access to data for heterogeneous workflows and applications while minimising data transfers across the different storage tiers. This deliverable introduces the software ecosystem of the EUPEX platform (cf. Fig. 1) and details how the above-mentioned challenges are met. Chapter 2 presents components of the management software stack. Chapter 3 introduces the fully MSA-aware execution environment enabling a flexible and efficient utilisation of the available resources within the EUPEX platform. Chapter 4 deals with tools for performance and energy efficiency that allow for monitoring and profiling the applications’ power/energy consumption and to determine performance bottlenecks. And finally, Chapter 5 presents the elements of the I/O system enabling fast and scalable access to data within the hierarchical storage system.
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- 2023
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13. A Topology-Aware Performance Monitoring Tool for Shared Resource Management in Multicore Systems
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Denoyelle, Nicolas, Goglin, Brice, Jeannot, Emmanuel, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Weikum, Gerhard, Series editor, Hunold, Sascha, editor, Costan, Alexandru, editor, Giménez, Domingo, editor, Iosup, Alexandru, editor, Ricci, Laura, editor, Gómez Requena, María Engracia, editor, Scarano, Vittorio, editor, Varbanescu, Ana Lucia, editor, Scott, Stephen L., editor, Lankes, Stefan, editor, Weidendorfer, Josef, editor, and Alexander, Michael, editor
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- 2015
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14. MBSPDiscover: An Automatic Benchmark for MultiBSP Performance Analysis
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Alaniz, Marcelo, Nesmachnow, Sergio, Goglin, Brice, Iturriaga, Santiago, Gosta, Veronica Gil, Printista, Marcela, Junqueira Barbosa, Simone Diniz, Series editor, Chen, Phoebe, Series editor, Cuzzocrea, Alfredo, Series editor, Du, Xiaoyong, Series editor, Filipe, Joaquim, Series editor, Kara, Orhun, Series editor, Kotenko, Igor, Series editor, Sivalingam, Krishna M., Series editor, Ślęzak, Dominik, Series editor, Washio, Takashi, Series editor, Yang, Xiaokang, Series editor, Hernández, Gonzalo, editor, Barrios Hernández, Carlos Jaime, editor, Díaz, Gilberto, editor, García Garino, Carlos, editor, Nesmachnow, Sergio, editor, Pérez-Acle, Tomás, editor, Storti, Mario, editor, and Vázquez, Mariano, editor
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- 2014
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15. Netloc: A Tool for Topology-Aware Process Mapping
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Bordage, Cyril, primary, Foyer, Clément, additional, and Goglin, Brice, additional
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- 2018
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16. Modeling Large Compute Nodes with Heterogeneous Memories with Cache-Aware Roofline Model
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Denoyelle, Nicolas, primary, Goglin, Brice, additional, Ilic, Aleksandar, additional, Jeannot, Emmanuel, additional, and Sousa, Leonel, additional
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- 2017
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17. H2M: Towards Heuristics for Heterogeneous Memory
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Klinkenberg, Jannis, Kozhokanova, Anara, Terboven, Christian, Foyer, Clément, Goglin, Brice, Jeannot, Emmanuel, Goglin, Brice, Heuristiques pour la mémoires hétérogènes - - H2M2020 - ANR-20-CE92-0022 - AAPG2020 - VALID, Rheinisch-Westfälische Technische Hochschule Aachen University (RWTH), Topology-Aware System-Scale Data Management for High-Performance Computing (TADAAM), Laboratoire Bordelais de Recherche en Informatique (LaBRI), Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS)-Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS)-Inria Bordeaux - Sud-Ouest, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria), and ANR-20-CE92-0022,H2M,Heuristiques pour la mémoires hétérogènes(2020)
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[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR] ,[INFO.INFO-AR] Computer Science [cs]/Hardware Architecture [cs.AR] ,Memory Heterogeneous Memory Non-Volatile Memory High-Bandwidth Memory Heuristics HPC Data Placement ,[INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation ,Memory ,[INFO.INFO-OS] Computer Science [cs]/Operating Systems [cs.OS] ,HPC ,[INFO.INFO-DC] Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC] ,Heuristics ,[INFO.INFO-OS]Computer Science [cs]/Operating Systems [cs.OS] ,[INFO.INFO-MO] Computer Science [cs]/Modeling and Simulation ,[INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC] ,Non-Volatile Memory ,High-Bandwidth Memory ,Data Placement ,Heterogeneous Memory - Abstract
International audience
- Published
- 2022
18. H2M: Towards Heuristics for Heterogeneous Memory
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Foyer, Clement, primary, Goglin, Brice, additional, Jeannot, Emmanuel, additional, Klinkenberg, Jannis, additional, Kozhokanova, Anara, additional, and Terboven, Christian, additional
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- 2022
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19. Adaptive MPI Multirail Tuning for Non-uniform Input/Output Access
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Moreaud, Stéphanie, Goglin, Brice, Namyst, Raymond, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Keller, Rainer, editor, Gabriel, Edgar, editor, Resch, Michael, editor, and Dongarra, Jack, editor
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- 2010
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20. NIC-Assisted Cache-Efficient Receive Stack for Message Passing over Ethernet
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Goglin, Brice, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Sips, Henk, editor, Epema, Dick, editor, and Lin, Hai-Xiang, editor
- Published
- 2009
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21. Dynamic Task and Data Placement over NUMA Architectures: An OpenMP Runtime Perspective
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Broquedis, François, Furmento, Nathalie, Goglin, Brice, Namyst, Raymond, Wacrenier, Pierre-André, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Müller, Matthias S., editor, de Supinski, Bronis R., editor, and Chapman, Barbara M., editor
- Published
- 2009
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22. An Efficient OpenMP Runtime System for Hierarchical Architectures
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Thibault, Samuel, Broquedis, François, Goglin, Brice, Namyst, Raymond, Wacrenier, Pierre-André, Hutchison, David, editor, Kanade, Takeo, editor, Kittler, Josef, editor, Kleinberg, Jon M., editor, Mattern, Friedemann, editor, Mitchell, John C., editor, Naor, Moni, editor, Nierstrasz, Oscar, editor, Pandu Rangan, C., editor, Steffen, Bernhard, editor, Sudan, Madhu, editor, Terzopoulos, Demetri, editor, Tygar, Doug, editor, Vardi, Moshe Y., editor, Weikum, Gerhard, editor, Chapman, Barbara, editor, Zheng, Weiming, editor, Gao, Guang R., editor, Sato, Mitsuhisa, editor, Ayguadé, Eduard, editor, and Wang, Dongsheng, editor
- Published
- 2008
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23. Using Performance Attributes for Managing Heterogeneous Memory in HPC Applications
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Goglin, Brice, primary and Proano, Andres Rubio, additional
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- 2022
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24. KNEM: A generic and scalable kernel-assisted intra-node MPI communication framework
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Goglin, Brice and Moreaud, Stéphanie
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- 2013
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25. High-performance message-passing over generic Ethernet hardware with Open-MX
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Goglin, Brice
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- 2011
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26. Using Bandwidth Throttling to Quantify Application Sensitivity to Heterogeneous Memory
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Foyer, Clement, primary and Goglin, Brice, additional
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- 2021
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27. A Topology-Aware Performance Monitoring Tool for Shared Resource Management in Multicore Systems
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Denoyelle, Nicolas, primary, Goglin, Brice, additional, and Jeannot, Emmanuel, additional
- Published
- 2015
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28. TEXTAROSSA: Towards EXtreme scale Technologies and Accelerators for euROhpc hw/Sw Supercomputing Applications for exascale
- Author
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Agosta, Giovanni, primary, Cattaneo, Daniele, additional, Fornaciari, William, additional, Galimberti, Andrea, additional, Massari, Giuseppe, additional, Reghenzani, Federico, additional, Terraneo, Federico, additional, Zoni, Davide, additional, Brandolese, Carlo, additional, Celino, Massimo, additional, Iannone, Francesco, additional, Palazzari, Paolo, additional, Zummo, Giuseppe, additional, Bernaschi, Massimo, additional, D'Ambra, Pasqua, additional, Saponara, Sergio, additional, Danelutto, Marco, additional, Torquati, Massimo, additional, Aldinucci, Marco, additional, Arfat, Yasir, additional, Cantalupo, Barbara, additional, Colonnelli, Iacopo, additional, Esposito, Roberto, additional, Martinelli, Alberto R., additional, Mittone, Gianluca, additional, Beaumont, Olivier, additional, Bramas, Berenger, additional, Eyraud-Dubois, Lionel, additional, Goglin, Brice, additional, Guermouche, Abdou, additional, Namyst, Raymond, additional, Thibault, Samuel, additional, Filgueras, Antonio, additional, Vidal, Miquel, additional, Alvarez, Carlos, additional, Martorell, Xavier, additional, Oleksiak, Ariel, additional, Kulczewski, Michal, additional, Lonardo, Alessandro, additional, Vicini, Piero, additional, Cicero, Francesca Lo, additional, Simula, Francesco, additional, Biagioni, Andrea, additional, Cretaro, Paolo, additional, Frezza, Ottorino, additional, Paolucci, Pier Stanislao, additional, Turisini, Matteo, additional, Giacomini, Francesco, additional, Boccali, Tommaso, additional, Montangero, Simone, additional, and Ammendola, Roberto, additional
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- 2021
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29. Profiles of Upcoming HPC Applications and Their Impact on Reservation Strategies
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Gainaru, Ana, primary, Goglin, Brice, additional, Honore, Valentin, additional, and Pallez, Guillaume, additional
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- 2021
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30. ForestGOMP: An Efficient OpenMP Environment for NUMA Architectures
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Broquedis, François, Furmento, Nathalie, Goglin, Brice, Wacrenier, Pierre-André, and Namyst, Raymond
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- 2010
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31. Profiles of upcoming HPC Applications and their Impact on Reservation Strategies
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Gainaru, Ana, Goglin, Brice, Honoré, Valentin, Pallez, Guillaume, Vanderbilt University [Nashville], Topology-Aware System-Scale Data Management for High-Performance Computing (TADAAM), Laboratoire Bordelais de Recherche en Informatique (LaBRI), Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Inria Bordeaux - Sud-Ouest, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria), Inria & Labri, Université Bordeaux, and Plafrim
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Execution time ,Stochastic application ,Plateformes de calcul ,Scheduling ,Checkpointing ,Point de sauvegarde ,Empreinte mémoire ,Coût stochastique ,Reservation sequence ,Ordonnancement ,Neuroscience application ,Reservation-based platform ,Memory footprint ,Applications de neurosciences ,[INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC] ,Stratégies de réservations - Abstract
With the expected convergence between HPC, BigData and AI, newapplications with different profiles are coming to HPC infrastructures.We aim at better understanding the features and needs of theseapplications in order to be able to run them efficiently on HPC platforms.The approach followed is bottom-up: we study thoroughly an emergingapplication, Spatially Localized Atlas Network (SLANT, originating from the neuroscience community) to understand its behavior.Based on these observations, we derive a generic, yet simple, application model (namely, a linear sequence of stochastic jobs). We expect this model to be representative for a large set of upcoming applicationsthat require the computational power of HPC clusters without fitting the typical behavior oflarge-scale traditional applications.In a second step, we show how one can manipulate this generic model in a scheduling framework. Specifically we consider the problem of making reservations (both time andmemory) for an execution on an HPC platform.We derive solutions using the model of the first step of this work.We experimentally show the robustness of the model, even with very few data or with another application, to generate themodel, and provide performance gains; La convergence entre les domaines du calcul haute-performance, du BigData et de l'intelligence artificiellefait émerger de nouveaux profils d'application sur les infrastructures HPC.Dans ce travail, nous proposons une étude de ces nouvelles applications afin de mieux comprendre leurs caractériques et besoinsdans le but d'optimiser leur exécution sur des plateformes HPC.Pour ce faire, nous adoptons une démarche ascendante. Premièrement, nous étudions en détail une application émergente, SLANT, provenant du domaine des neurosciences. Par un profilage détaillé de l'application, nous exposons ses principales caractéristiques ainsi que ses besoins en terme de ressources de calcul.A partir de ces observations, nous proposons un modèle d'application générique, pour le moment simple, composé d'une séquence linéaire de tâches stochastiques. Ce modèle devrait, selon nous, être adapté à une grande variété de ces applications émergentes qui requièrent la puissance de calcul des clusters HPC sans présenter le comportement typique des applications qui s'exécutent sur des machines à grande-échelle.Deuxièmement, nous montrons comment utiliser le modèle d'application générique dans le cadre du développement de stratégies d'ordonnancement. Plus précisément, nous nous intéressons à la conception de stratégies de réservations (à la fois en terme de temps de calcul et de mémoire).Nous proposons de telles solutions utilisant le modèle d'application générique exprimé dans la première étape de ce travail.Enfin, nous montrons la robustesse du modèle d'application et de nos stratégies d'ordonnancement au travers d'évaluations expérimentales de nos stratégies.Notamment, nous démontrons que nos solutions surpassent les approches standards de la communauté des neurosciences, même en cas de donnéespartielles ou d'extension à d'autres applications que SLANT.
- Published
- 2020
32. Etude d’applications émergentes en HPC et leurs impacts sur des stratégies d’ordonnancement
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Gainaru, Ana, Goglin, Brice, Honoré, Valentin, Pallez, Guillaume, Vanderbilt University [Nashville], Topology-Aware System-Scale Data Management for High-Performance Computing (TADAAM), Laboratoire Bordelais de Recherche en Informatique (LaBRI), Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Inria Bordeaux - Sud-Ouest, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria), Inria & Labri, Université Bordeaux, Plafrim, and Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS)-Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS)-Inria Bordeaux - Sud-Ouest
- Subjects
Execution time ,Stochastic application ,Plateformes de calcul ,Scheduling ,Checkpointing ,Point de sauvegarde ,Empreinte mémoire ,Coût stochastique ,Reservation sequence ,Ordonnancement ,Neuroscience application ,Reservation-based platform ,Memory footprint ,Applications de neurosciences ,[INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC] ,Stratégies de réservations - Abstract
With the expected convergence between HPC, BigData and AI, newapplications with different profiles are coming to HPC infrastructures.We aim at better understanding the features and needs of theseapplications in order to be able to run them efficiently on HPC platforms.The approach followed is bottom-up: we study thoroughly an emergingapplication, Spatially Localized Atlas Network (SLANT, originating from the neuroscience community) to understand its behavior.Based on these observations, we derive a generic, yet simple, application model (namely, a linear sequence of stochastic jobs). We expect this model to be representative for a large set of upcoming applicationsthat require the computational power of HPC clusters without fitting the typical behavior oflarge-scale traditional applications.In a second step, we show how one can manipulate this generic model in a scheduling framework. Specifically we consider the problem of making reservations (both time andmemory) for an execution on an HPC platform.We derive solutions using the model of the first step of this work.We experimentally show the robustness of the model, even with very few data or with another application, to generate themodel, and provide performance gains; La convergence entre les domaines du calcul haute-performance, du BigData et de l'intelligence artificiellefait émerger de nouveaux profils d'application sur les infrastructures HPC.Dans ce travail, nous proposons une étude de ces nouvelles applications afin de mieux comprendre leurs caractériques et besoinsdans le but d'optimiser leur exécution sur des plateformes HPC.Pour ce faire, nous adoptons une démarche ascendante. Premièrement, nous étudions en détail une application émergente, SLANT, provenant du domaine des neurosciences. Par un profilage détaillé de l'application, nous exposons ses principales caractéristiques ainsi que ses besoins en terme de ressources de calcul.A partir de ces observations, nous proposons un modèle d'application générique, pour le moment simple, composé d'une séquence linéaire de tâches stochastiques. Ce modèle devrait, selon nous, être adapté à une grande variété de ces applications émergentes qui requièrent la puissance de calcul des clusters HPC sans présenter le comportement typique des applications qui s'exécutent sur des machines à grande-échelle.Deuxièmement, nous montrons comment utiliser le modèle d'application générique dans le cadre du développement de stratégies d'ordonnancement. Plus précisément, nous nous intéressons à la conception de stratégies de réservations (à la fois en terme de temps de calcul et de mémoire).Nous proposons de telles solutions utilisant le modèle d'application générique exprimé dans la première étape de ce travail.Enfin, nous montrons la robustesse du modèle d'application et de nos stratégies d'ordonnancement au travers d'évaluations expérimentales de nos stratégies.Notamment, nous démontrons que nos solutions surpassent les approches standards de la communauté des neurosciences, même en cas de donnéespartielles ou d'extension à d'autres applications que SLANT.
- Published
- 2020
33. Reservation and Checkpointing Strategies for Stochastic Jobs (Extended Version)
- Author
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Gainaru, Ana, Goglin, Brice, Honoré, Valentin, Pallez, Guillaume, Raghavan, Padma, Robert, Yves, Sun, Hongyang, Vanderbilt University [Nashville], Topology-Aware System-Scale Data Management for High-Performance Computing (TADAAM), Laboratoire Bordelais de Recherche en Informatique (LaBRI), Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Inria Bordeaux - Sud-Ouest, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria), Optimisation des ressources : modèles, algorithmes et ordonnancement (ROMA), Inria Grenoble - Rhône-Alpes, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-Laboratoire de l'Informatique du Parallélisme (LIP), École normale supérieure - Lyon (ENS Lyon)-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Université de Lyon-Institut National de Recherche en Informatique et en Automatique (Inria)-Centre National de la Recherche Scientifique (CNRS)-École normale supérieure - Lyon (ENS Lyon)-Université Claude Bernard Lyon 1 (UCBL), Université de Lyon-Université de Lyon-Centre National de la Recherche Scientifique (CNRS), Inria & Labri, Univ. Bordeaux, Department of EECS, Vanderbilt University, Nashville, TN, USA, and Laboratoire LIP, ENS Lyon & University of Tennessee Knoxville, Lyon, France
- Subjects
Plateformes de calcul ,Scheduling ,[INFO.INFO-DS]Computer Science [cs]/Data Structures and Algorithms [cs.DS] ,Checkpointing ,Neuroscience applications ,Point de sauvegarde ,Sequence of requests ,Séquence de réservations ,Stochastic cost ,Coût stochastique ,Ordonnancement ,Computing platform ,Applications de neurosciences ,[INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC] - Abstract
In this work, we are interested in scheduling and checkpointing stochastic jobs ona reservation-based platform. We assume that jobs can be interrupted at any time to take acheckpoint, and that job execution times follow a known probability distribution. The user has todetermine a sequence of fixed-length reservation requests, and to decide whether to checkpoint thestate of the execution, or not, at the end of each request. The execution of the job is successful onlywhen it terminates within a request, otherwise it must be resubmitted, using the next request in thereservation sequence, and restarting execution from the last checkpointed state. The cost of eachreservation depends on both its duration and on the actual utilization of the platform during thatrequest, which includes a restart if some previous reservation was terminated with a checkpoint, andpossibly a checkpoint at the end of the current request. The cost of a job is then the cumulatedcost of all the reservations that were needed until its completion. Overall, the objective is tofind a reservation sequence that minimizes the total expected cost to execute a job. We providean optimal strategy for discrete probability distributions of job execution times, and we designfully polynomial-time approximation strategies for continuous distributions with bounded support.We experimentally evaluate these strategies for jobs following a wide range of usual probabilitydistributions, as well as one distribution obtained from traces of a neuroscience application. Wecompare our strategies with standard approaches that use periodic-length reservations (the nextreservation is longer than the previous one by a constant amount of time) and simple checkpointingstrategies (either checkpoint all reservations, or none).; Dans ce rapport, nous nous intéressons à l’ordonnancement de tâches stochastiques exécutées sur une plateforme à réservations, où l’utilisateur réalise des requêtes successives de temps de calcul. Le temps d’exécution des tâches considérées n’est pas connu à l’avance. Ce temps estreprésenté par une loi de probabilité, décrite sous la forme d’une densité de probabilité. Nous nous intéressons à ordonnancer une instance d’une telle tâche, c’est à dire que nous ne connaissons pas son temps d’exécution qui reste constant tout au long de l’ordonnancement. Dans ce cas, lecoût de l’ordonnancement dépend à la fois de la durée des requêtes et du temps d’exécution de la tâche considérée.Nous supposons de plus que la tâche peut être interrompue à tout instant (tâche divisible) pour un point de sauvegarde. Nous avons donc la possibilité de prendre un point de sauvegarde à la fin de certaines réservations bien choisies. L’avantage est de pouvoir repartir de l’étatsauvegardé à la prochaine réservation au lieu de repartir du début, si la tâche ne termine pas pendant la réservation courante. Le prix à payer est le temps de sauvegarde, et de redémarrage.L’objectif de ce travail est de déterminer une stratégie de réservation optimale qui minimise le coût total de l’ordonnancement. Une stratégie de réservations est une séquence de requêtes croissantes, qui sont payées les unes à la suite des autres en ordre croissant jusqu’à complétionde la tâche. Pour chaque réservation, nous indiquons si un point de sauvegarde doit être pris ou non.Nous décrivons une telle solution optimale pour des distributions de probabilité discrètes, et nous donnons un schéma d’approximation polynomial pour les distributions continues à support compact. Nous comparons expérimentalement ces stratégies aux stratégies usuelles qui incrémentent la longueur de chaque réservation par une valeur constante, et qui décident de sauvegarder soit toutes les réservations, soit aucune. Nous utilisons un grand nombre de lois de probabilité usuelles (i.e. Uniforme, Exponentielle, Log-Normale, Weibull, Beta etc), ainsi qu’une distribution basée sur l’interpolation de traces d’applications de neurosciences exécutées sur une plateforme HPC.
- Published
- 2019
34. Computing Networks
- Author
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Vicat-Blanc, Pascale, primary, Soudan, Sébastien, additional, Guillier, Romaric, additional, and Goglin, Brice, additional
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- 2013
- Full Text
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35. Application-Driven Requirements for Node Resource Management in Next-Generation Systems
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Leon, Edgar A., primary, Gerofi, Balazs, additional, Jaeger, Julien, additional, Mercier, Guillaume, additional, Riesen, Rolf, additional, Takagi, Masamichi, additional, and Goglin, Brice, additional
- Published
- 2020
- Full Text
- View/download PDF
36. Introduction
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Träff, Jesper Larsson, primary, Goglin, Brice, additional, Bruening, Ulrich, additional, and Petrini, Fabrizio, additional
- Published
- 2011
- Full Text
- View/download PDF
37. Adaptive MPI Multirail Tuning for Non-uniform Input/Output Access
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Moreaud, Stéphanie, primary, Goglin, Brice, additional, and Namyst, Raymond, additional
- Published
- 2010
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- View/download PDF
38. Introduction
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Träff, Jesper Larsson, Goglin, Brice, Bruening, Ulrich, Petrini, Fabrizio, Hutchison, David, Series editor, Kanade, Takeo, Series editor, Kittler, Josef, Series editor, Kleinberg, Jon M., Series editor, Mattern, Friedemann, Series editor, Mitchell, John C., Series editor, Naor, Moni, Series editor, Nierstrasz, Oscar, Series editor, Pandu Rangan, C., Series editor, Steffen, Bernhard, Series editor, Sudan, Madhu, Series editor, Terzopoulos, Demetri, Series editor, Tygar, Doug, Series editor, Vardi, Moshe Y., Series editor, Weikum, Gerhard, Series editor, Jeannot, Emmanuel, editor, Namyst, Raymond, editor, and Roman, Jean, editor
- Published
- 2011
- Full Text
- View/download PDF
39. Dynamic Task and Data Placement over NUMA Architectures: An OpenMP Runtime Perspective
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Broquedis, François, primary, Furmento, Nathalie, additional, Goglin, Brice, additional, Namyst, Raymond, additional, and Wacrenier, Pierre-André, additional
- Published
- 2009
- Full Text
- View/download PDF
40. Reservation and Checkpointing Strategies for Stochastic Jobs
- Author
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Gainaru, Ana, primary, Goglin, Brice, additional, Honore, Valentin, additional, Pallez Aupy, Guillaume, additional, Raghavan, Padma, additional, Robert, Yves, additional, and Sun, Hongyang, additional
- Published
- 2020
- Full Text
- View/download PDF
41. Modeling HPC applications for in situ Analytics
- Author
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Honoré, Valentin, Goglin, Brice, Aupy, Guillaume, Raffin, Bruno, Laboratoire Bordelais de Recherche en Informatique (LaBRI), Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS), Topology-Aware System-Scale Data Management for High-Performance Computing (TADAAM), Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS)-Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS)-Inria Bordeaux - Sud-Ouest, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria), Data Aware Large Scale Computing (DATAMOVE ), Inria Grenoble - Rhône-Alpes, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria)-Laboratoire d'Informatique de Grenoble (LIG ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019])-Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Laboratoire d'Informatique de Grenoble (LIG ), Institut polytechnique de Grenoble - Grenoble Institute of Technology (Grenoble INP )-Centre National de la Recherche Scientifique (CNRS)-Université Grenoble Alpes [2016-2019] (UGA [2016-2019]), Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB), and Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Inria Bordeaux - Sud-Ouest
- Subjects
[INFO]Computer Science [cs] ,[INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC] ,ComputingMilieux_MISCELLANEOUS - Abstract
International audience
- Published
- 2019
42. Programming Abstractions for Data Locality
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Tate, Adrian, primary, Kamil, Amir, additional, Dubey, Anshu, additional, Groblinger, Armin, additional, Chamberlain, Brad, additional, Goglin, Brice, additional, Edwards, Harold, additional, Newburn, Chris, additional, Padua, David, additional, Unat, Didem, additional, Jeannot, Emmanuel, additional, Hannig, Frank, additional, Tobias, Gysi, additional, Ltaief, Hatem, additional, Sexton, James, additional, Labarta, Jesus, additional, Shalf, John, additional, Fuerlinger, Karl, additional, O'Brien, Kathryn, additional, Linardakis, Leonidas, additional, Besta, Maciej, additional, Sawley, Marie-Christine, additional, Abraham, Mark, additional, Bianco, Mauro, additional, Pericas, Miquel, additional, Maruyama, Naoya, additional, Kelly, Paul, additional, Messmer, Peter, additional, Ross, Robert, additional, Ciedat, Romain, additional, Matsuoka, Satoshi, additional, Schulthess, Thomas, additional, Hoefler, Torsten, additional, and Leung, Vitus, additional
- Published
- 2014
- Full Text
- View/download PDF
43. Un modèle hièrarchique pour la gestion de la topologie dans les applications MPI
- Author
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Goglin, Brice, Jeannot, Emmanuel, Mansouri, Farouk, Mercier, Guillaume, Topology-Aware System-Scale Data Management for High-Performance Computing (TADAAM), Laboratoire Bordelais de Recherche en Informatique (LaBRI), Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Inria Bordeaux - Sud-Ouest, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria), Inria Bordeaux Sud-Ouest, Bordeaux INP, LaBRI - Laboratoire Bordelais de Recherche en Informatique, ANR-13-INFR-0001,MOEBUS,Gestion de ressources multi-objectifs pour plates-formes de calcul à large échelle(2013), and Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS)-Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS)-Inria Bordeaux - Sud-Ouest
- Subjects
Hardware Topology ,Hierarchy ,Message Passing ,[INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC] ,Passage de Messages ,Hiérarchie ,Topologie Matérielle - Abstract
The MPI standard is a major contribution in the landscape of parallel programming. Since its inception in the mid 90's it has ensured portability and performance for parallel applications on a wide spectrum of machines and architectures. With the advent of multicore machines, understanding and taking into account the underlying physical topology and memory hierarchy as become of paramount importance. The MPI standard in its current state, however, and despite recent evolutions is still unable to offer mechanisms to achieve this. In this paper, we detail several additions to the standard that give the user tools to address the hardware topology and data locality issues while improving application performance.; Le standard MPI est une contribution importante dans le domaine de la programmation parallèle. Il est destiné à l'écriture d'applications parallèles pour un large éventail d'architectures parallèles. L'arrivée des machines multicœur implique une compréhension plus fine de la topologie matérielle sous-jacente, notamment en ce qui concerne les hiérarchies mémoire et réseau. Or, dans son statut actuel, MPI ne permet pas de prendre ces aspects en compte. Nous détaillons dans cet article des modifications à MPI pour permettre la prise en compte de ces aspects afind'améliorer les performances applicatives.
- Published
- 2018
44. A Hierarchical Model to Manage Hardware Topology in MPI Applications
- Author
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Goglin, Brice, Jeannot, Emmanuel, Mansouri, Farouk, Mercier, Guillaume, Topology-Aware System-Scale Data Management for High-Performance Computing (TADAAM), Laboratoire Bordelais de Recherche en Informatique (LaBRI), Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Inria Bordeaux - Sud-Ouest, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria), Inria Bordeaux Sud-Ouest, Bordeaux INP, LaBRI - Laboratoire Bordelais de Recherche en Informatique, and ANR-13-INFR-0001,MOEBUS,Gestion de ressources multi-objectifs pour plates-formes de calcul à large échelle(2013)
- Subjects
Hardware Topology ,Hierarchy ,Message Passing ,[INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC] ,Passage de Messages ,Hiérarchie ,Topologie Matérielle - Abstract
The MPI standard is a major contribution in the landscape of parallel programming. Since its inception in the mid 90's it has ensured portability and performance for parallel applications on a wide spectrum of machines and architectures. With the advent of multicore machines, understanding and taking into account the underlying physical topology and memory hierarchy as become of paramount importance. The MPI standard in its current state, however, and despite recent evolutions is still unable to offer mechanisms to achieve this. In this paper, we detail several additions to the standard that give the user tools to address the hardware topology and data locality issues while improving application performance.; Le standard MPI est une contribution importante dans le domaine de la programmation parallèle. Il est destiné à l'écriture d'applications parallèles pour un large éventail d'architectures parallèles. L'arrivée des machines multicœur implique une compréhension plus fine de la topologie matérielle sous-jacente, notamment en ce qui concerne les hiérarchies mémoire et réseau. Or, dans son statut actuel, MPI ne permet pas de prendre ces aspects en compte. Nous détaillons dans cet article des modifications à MPI pour permettre la prise en compte de ces aspects afind'améliorer les performances applicatives.
- Published
- 2018
45. M&MMs
- Author
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León, Edgar A., primary, Goglin, Brice, additional, and Proaño, Andres Rubio, additional
- Published
- 2019
- Full Text
- View/download PDF
46. Data and Thread Placement in NUMA Architectures
- Author
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Denoyelle, Nicolas, primary, Goglin, Brice, additional, Jeannot, Emmanuel, additional, and Ropars, Thomas, additional
- Published
- 2019
- Full Text
- View/download PDF
47. Modeling Non-Uniform Memory Access on Large Compute Nodes with the Cache-Aware Roofline Model
- Author
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Denoyelle, Nicolas, primary, Goglin, Brice, additional, Ilic, Aleksandar, additional, Jeannot, Emmanuel, additional, and Sousa, Leonel, additional
- Published
- 2019
- Full Text
- View/download PDF
48. Modeling high-throughput applications for in situ analytics
- Author
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Aupy, Guillaume, primary, Goglin, Brice, additional, Honoré, Valentin, additional, and Raffin, Bruno, additional
- Published
- 2019
- Full Text
- View/download PDF
49. Co-scheduling HPC workloads on cache-partitioned CMP platforms
- Author
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Aupy, Guillaume, primary, Benoit, Anne, additional, Goglin, Brice, additional, Pottier, Loïc, additional, and Robert, Yves, additional
- Published
- 2019
- Full Text
- View/download PDF
50. Towards the Structural Modeling of the Topology of next-generation heterogeneous cluster Nodes with hwloc
- Author
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Goglin, Brice, Topology-Aware System-Scale Data Management for High-Performance Computing (TADAAM), Laboratoire Bordelais de Recherche en Informatique (LaBRI), Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS)-Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS)-Inria Bordeaux - Sud-Ouest, Institut National de Recherche en Informatique et en Automatique (Inria)-Institut National de Recherche en Informatique et en Automatique (Inria), Université de Bordeaux (UB)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Centre National de la Recherche Scientifique (CNRS), Inria, plafrim, Mésocentre de Calcul Intensif Aquitain, Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)-Inria Bordeaux - Sud-Ouest, and Université de Bordeaux (UB)-Centre National de la Recherche Scientifique (CNRS)-École Nationale Supérieure d'Électronique, Informatique et Radiocommunications de Bordeaux (ENSEIRB)
- Subjects
[INFO.INFO-AR]Computer Science [cs]/Hardware Architecture [cs.AR] ,[INFO.INFO-OS]Computer Science [cs]/Operating Systems [cs.OS] ,[INFO.INFO-DC]Computer Science [cs]/Distributed, Parallel, and Cluster Computing [cs.DC] ,[INFO.INFO-MO]Computer Science [cs]/Modeling and Simulation - Abstract
Parallel computing platforms are increasingly complex, with multiple cores, shared caches, and NUMA memory interconnects, as well as asymmetric I/O access. Upcoming architectures will add a heterogeneous memory subsystem with non-volatile and/or high-bandwidth memory banks. Parallel applications developers have to take locality into account before they can expect good efficiency on these platforms. Thus there is a strong need for a portable tool gathering and exposing this information. The Hardware Locality project (hwloc) offers a tree representation of the hardware based on the inclusion of CPU resources and localities of memory and I/O devices. It is already widely used for affinity-based task placement in high performance computing. We present how hwloc represents parallel computing nodes, from the hierarchy of computing and memory resources to I/O device locality. It builds a structural model of the hardware to help application find the best resources fitting their needs. hwloc also annotates objects to ease identification of resources from different programming points of view. We finally describe how it helps process managers and batch schedulers to deal with the topology of multiple cluster nodes, by offering different compression techniques for better management of thousands of nodes.
- Published
- 2016
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