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Industrial motion control systems, e.g. pick-andplace tasks in semiconductor manufacturing equipment, require precise positioning for achieving high machine throughput. Linear encoders are the standard industrial sensors used for position feedback due to their relatively low cost, high resolution, and high operating frequency. The challenge is that the linear encoders measure the positions at the points-ofcontrol of the equipment, e.g. motors, and not at the points-ofinterest, e.g. pick-and-place positions. The coupling between a point-of-control and the point-of-interest is affected by external disturbances such as mechanical misalignment of the product, friction, and warping of the material, and linear encoders fail to sense these disturbances. Vision-based sensing is a potential alternative to achieve robust sensing and high-precision control. However, vision processing has a long computational delay and affects the machine throughput. In this paper, we propose a multi-rate multi-sensor fusion approach to improve the positioning accuracy of industrial motion control systems with different points-of-control and points-of-interest. We present a multi-rate Kalman filter with bias correction to fuse accurate but slow and delayed vision sensor data with fast but less accurate linear encoder data for highprecision position control. We validate the proposed method in an evaluation framework by considering an industrial case study of a semiconductor die-bonding machine. A design-space exploration is done to evaluate the performance of the proposed solution with respect to various relevant design parameters. The effectiveness of the proposed solution depends on the type of disturbances and vision processing delay. For the parameter range under consideration, we achieve a positioning accuracy of 1μm.

As a transparent communication protocol for concurrent distributed applications, the Publish-Subscribe (Pub-Sub) paradigm is a trending programming model in many recent industrial use-cases in robotics and avionics. To apply the Pub-Sub programming model for safety-critical concurrent realtime applications in Multi-Processor Systems on Chip (MPSoC) environments, a non-blocking wait-free First-In-First-Out (FIFO) channel is a fundamental requirement. However, the proposed approaches in the literature have no proven real-time guarantees. In this paper, we propose a novel wait-free FIFO approach for single-producer-single-consumer core-to-core communication through shared memory. By analyzing the execution paths of each involved process, we prove that the execution time of each read/write operation is bounded by a Worst Case Execution Time (WCET). Moreover, we define a Timed Automata model of our approach. Using the UPPAAL model checker, we prove freedom of deadlock and starvation. For the performance evaluation of the proposed approach, we apply a stochastic analysis technique on the defined UPPAAL model. Finally, we implement the proposed approach on the CompSOC platform as the underlying realtime MPSoC to show that the implementation conforms to the proposed formal model and to experimentally validate the formal properties. The experimental evaluation on an instance of CompSOC that works at 40 MHz has a throughput of 109K tokens per second.

Traditional embedded systems and recent platforms used in emerging computing paradigms (e.g., fog computing) have resource limits and require their applications and services to be dynamically added (i.e., deployed) and removed at run-time. These applications often have non-functional (quality) requirements (e.g., end-to-end latency) which are only satisfied when sufficient resources are allocated to them. Hence, a run-time decision-maker is needed to optimize the deployments, in terms of resource budgets that are allocated to applications. Additionally, computing platforms have become heterogeneous in terms of their resources and the applications they execute. However, the existing deployment solutions are limited to specific resources and services. In this paper, we propose a run-time deployment framework that is more flexible in defining constraints and optimization goals and works with more heterogeneous resources and resource models than existing solutions. The framework is implemented on an embedded platform as a proof of concept.

Robot Operating System (ROS) is a de-facto standard robot middleware in many academic and industrial use cases. However, utilizing ROS/ROS2 in safety-critical embedded applications with real-time requirement is challenging because of C1) Non-real-time underlying hardware, C2) No control on the host OS scheduler, C3) Unpredictable dynamic memory allocation, C4) High resource requirement, and C5) Unpredictable execution model for ROS nodes. In this paper, we address these limiting factors by proposing a hardware-software architecture -CompROS- for ROS2 based robotic development in a Multi-Processor System on Chip (MPSoC) platform that. The proposed hardware architecture consists of a Hard Real-Time (HRT) RISC-V based subsystem implemented in the Programmable Logic (PL) part of the MPSoC platform, a Soft Real-Time (SRT) ARM-based subsystem in the Processing System (PS) part of the MPSoC platform, and a Non-Real-Time (NRT) PC. While the proposed hardware architecture along with a partitioning layer overcomes the first two limiting factors, the rest are managed by the proposed multi-layer software architecture. We make a bare-metal implementation of XRCE-DDS standard for PL-PS communication, while peer-to-peer PL-PL communication is done through a proposed real-time publish-subscribe approach. The reliable communication for PS-PLL communication is done through utilizing C-HEAP protocol. Further, we integrate ROS2 software layers on top of the proposed hardware and software layers. Finally, with respect to C5, we present a real-time execution model of ROS2 nodes by a mapping of ROS2 entities to CompROS entities, which is validated through experimental results. We run ROS2 middleware with an executable size of less than 200 KB on an MPSoC platform.

Matlab provides an environment to analyse and visualise data and develop algorithms. However, there is limited support for visualising and analysing system activities executing concurrently, for instance, on a multiprocessor platform. Trace (https://esi.nl/research/output/tools/trace) is software that specialises in visualising and analysing concurrent system activities and execution traces. We present a Matlab to Trace translator that directly generates a trace-input file from the Matlab environment. Concurrent system activities and execution traces of the algorithms developed inside the Matlab environment can be visualised and analysed in Trace using the generated trace-input file. The translator takes as input the logical or absolute starting and ending time of the algorithmic execution, and the number (and labels) of processing cores. TRACE visualizes concurrent activities in a Gantt-chart-like view which provides colouring, grouping and filtering options. TRACE also provides several analysis methods, which sets it apart from the many other Gantt-chart visualization tools: i) Critical-path analysis can be used to detect tasks and resources that are bottlenecks for performance; ii) Distance analysis can be used to compare execution traces with respect to structure, e.g. to check a model trace against an implementation trace; iii) MTL checking provides a means to formally specify and verify properties of execution traces using Metric Temporal Logic. It is useful to express and check, for instance, performance properties such as the “processing latency is at most 50 ms”; iv) The streaming performance DSL is a domain-specific language that captures often-used performance properties for stream-processing systems (e.g., image or video processing), and which eases the use of the MTL checker; and v) The resource usage feature can quickly give insight in the details of the resource usage. The Matlab2Trace can be downloaded from https://github.com/TUE-EE-ES/Matlab2Trace.

Cyber-Physical Systems (CPS) are dynamic and reactive systems interacting with processes, environment and, sometimes, humans. They are often distributed with sensors and actuators, smart, adaptive, predictive and react in real-Time. Indeed, as sight for human beings, image-and video-processing pipelines are a prime source for environmental information for systems allowing them to take better decisions according to what they see. Therefore, in FitOptiVis we are developing novel methods and tools to integrate complex image and video processing pipelines. FitOptiVis aims to deliver a reference architecture for describing and optimizing quality and resource management for imaging and video pipelines in CPS both at design-and run-Time. The architecture is concretized in low-power, high-performance, smart components, and in methods and tools for combined design-Time and run-Time multi-objective optimization and adaptation within system and environment constraints.

This paper presents design and implementation techniques for iterative learning controllers (ILCs) targeting predictable multi-core embedded platforms. Implementation on embedded platforms results in a number of timing artifacts. Sensor-to-actuator delay (referred to as delay) is an important timing artifact which influences the control performance by changing the dynamic behavior of the system. We propose a delay-based design for ILCs that identifies and operates in the performance-optimal delay region. We then propose two implementation methods - sequential and parallel - for ILCs targeting the predictable multi-core platforms. The proposed methods enable the designer to carefully adjust the scheduling to achieve the optimal delay region in the resulting control system. We validate our results by the hardware-in-the-loop (HIL) simulation, considering a motion system as a case-study. Index Terms - Embedded control, Iterative learning control, Sensor-to-actuator-delay, Predictable multi-core platform.

Image-based control (IBC) systems use camera sensor(s) to perceive the environment. The inherent compute-heavy nature of image processing causes long processing delay that negatively influences the performance of the IBC systems. Our idea is to reduce the long delay using coarse-grained approximation of the image signal processing pipeline without affecting the functionality and performance of the IBC system. The question is: how is the degree of approximation related to the closed-loop quality-of-control (QoC), memory utilization and energy consumption? We present a software-in-the-loop (SiL) evaluation framework for the above approximation-in-the-loop system. We identify the error resilient stages and the corresponding coarse-grained approximation settings for the IBC system. We perform trade off analysis between the QoC, memory utilisation and energy consumption for varying degrees of coarse-grained approximation. We demonstrate the effectiveness of our approach using a concrete case study of a lane keeping assist system (LKAS). We obtain energy and memory reduction of upto 84% and 29% respectively, for 28% QoC improvements.

Timing properties of applications strongly depend on resources that are allocated to them. Applications often have multiple resource requirements, all of which must be met for them to proceed. Performance analysis of event-based systems has been widely studied in the literature. However, the proposed works consider only one resource requirement for each application task. Additionally, they mainly focus on the rate at which resources serve applications (e.g., power, instructions or bits per second), but another aspect of resources, which is their provided capacity (e.g., energy, memory ranges, FPGA regions), has been ignored. In this work, we propose a mathematical framework to describe the provisioning rate and capacity of various types of resource. Additionally, we consider the simultaneous use of multiple resources. Conservative bounds on response times of events and their backlog are computed. We prove that the bounds are monotone in event arrivals and in required and provided rate and capacity, which enables verification of real-time application performance based on worst-case characterizations. The applicability of our framework is shown in a case study.

Modern high-tech flexible manufacturing systems (FMS) such as lithography systems, professional printers, X-ray machines, and electron microscopes are characterized by an increasingly tight coupling between machine control software and the controlled physical processes. Control software and the design and configuration of FMS have an important impact on system productivity and product quality. Model-based, scenario-based design provides means for guaranteeing and optimizing system productivity while ensuring its proper functioning. We show that abstract system-level activity models, semantically grounded in (max,+) algebra with activities capturing execution scenarios of the FMS, can be used for fast and accurate productivity analysis of FMS in early design phases. The same models can be used for supervisory controller synthesis and optimization, providing safety and performance guarantees in the supervisory control software. Finally, scenario-based, adaptive, pipelined control enables optimization of data-intensive control loops in FMS, which in turn impacts system-level productivity.

This paper presents a model-based PIL simulation framework targeting multi-core multi-application FPGA-based embedded platforms. The process from model-based simulations to implementing on the platform requires a target specified code generation, compile and execution. The presented framework is able to automatically go through this process and perform the PIL simulation starting from a model-based environment in particular Simulink. It is also able to consider the multi-application nature of the target platform, executing the PIL simulation without interfering other applications. We validate the functionality of the PIL framework by testing a control systems application, using various PIL configurations.

From model-based design to implementation on an embedded platform requires target-specific code generation, compilation, and execution. Processor-in-the-loop (PIL) simulation is an intermediate step meant for detailed testing and debugging in the development process. This paper presents a PIL simulation framework targeting multi-core FPGA-based embedded platforms. The presented framework allows for a fully automated process of performing PIL simulations on an FPGA-based embedded platform - CompSOC - starting from a Simulink model. The framework includes two PIL configurations - one configuration executes only the controller code on the target platform while other configuration executes both the controller and the plant code on the target platform. It considers scheduling of multiple applications and interference-free execution on the target platform under the PIL configurations. Further, the framework allows for logging various measurements of parameters such as execution time, memory usage and so on in the PIL configurations which can be used for testing and debugging purposes.

This paper performs a feasibility analysis of deploying Model Predictive Control (MPC) for vehicle platooning on an On-Board Unit (OBU) and performance benchmarking considering interference from other (system) tasks running on an OBU. MPC is a control strategy that solves an implicit (on-line) or explicit (off-line) optimisation problem for computing the control input in every sample. OBUs have limited computational resources. The challenge is to implement an MPC algorithm on such automotive Electronic Control Units (ECUs) with an acceptable timing behavior. Moreover, we should be able to stop the execution if necessary at the cost of performance. We measured the computational capability of a unit developed by Cohda Wireless and NXP under the influence of its Operating System (OS). Next, we analysed the computational requirements of different state-of-the-art MPC algorithms by estimating their execution times. We use off-the-shelf and free automatic code generators for MPC to run a number of relevant MPC algorithms on the platform. From the results, we conclude that it is feasible to implement MPC on automotive ECUs for vehicle platooning and we further benchmark their performance in terms of MPC parameters such as prediction horizon and system dimension.