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Graphene is a promising material for applications as a channel in graphene field-effect transistors (GFETs) which may be used as a building block for optoelectronics, high-frequency devices and sensors. However, these devices require gate insulators which ideally should form atomically flat interfaces with graphene and at the same time contain small densities of traps to maintain high device stability. Previously used amorphous oxides, such as SiO2 and Al2O3, however, typically suffer from oxide dangling bonds at the interface, high surface roughness and numerous border oxide traps. In order to address these challenges, here we use 2 nm thick epitaxial CaF2 as a gate insulator in GFETs. By analyzing device-to-device variability for about 200 devices fabricated in two batches, we find that tens of them show similar gate transfer characteristics. Our statistical analysis of the hysteresis up to 175oC has revealed that while an ambient-sensitive counterclockwise hysteresis can be present in some devices, the dominant mechanism is thermally activated charge trapping by border defects in CaF2 which results in the conventional clockwise hysteresis. We demonstrate that both the hysteresis and bias-temperature instabilities in our GFETs with CaF2 are comparable to similar devices with SiO2 and Al2O3. In particular, we achieve a small hysteresis below 0.01 V for equivalent oxide thickness (EOT) of about 1 nm at the electric fields up to 15 MV cm−1 and sweep times in the kilosecond range. Thus, our results demonstrate that crystalline CaF2 is a promising insulator for highly-stable GFETs. [ABSTRACT FROM AUTHOR]

Recent advances in fabricating field-effect transistors with MoS2 and other related two-dimensional (2D) semiconductors have inspired the industry to begin with the integration of these emerging technologies into FAB-compatible process flows. Just like in the lab research on 2D devices performed in the last decade, focus during development is typically put on pure technology-related issues, such as low-temperature growth methods of large-area 2D films on target substrates, damage-free transfer from sacrificial substrates and growth of top-gate oxides. With maturing technology, the problem of stability limitations caused by oxide traps is gradually coming into focus now. Thus, here we report an in-depth analysis of hysteresis and bias-temperature instabilities for MoS2 FETs fabricated using a 300 mm FAB-compatible process. By performing a comprehensive statistical analysis on devices with top gate lengths ranging between 18 nm and 10 μm, we demonstrate that aggressive scaling results in additional stability problems, likely caused by defective edges of the scaled top gates, in particular at higher operation temperatures. These are important insights for understanding and addressing the stability limitations in future nanoscale 2D FETs produced using FAB process lines. [ABSTRACT FROM AUTHOR]