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A significant performance limitation in integrated circuits has become the metal interconnect, which is responsible for depressing the on-chip data bandwidth while consuming an increasing percentage of power. These problems will grow as wire diameters scale down and the resistance-capacitance product of the interconnect wires increases hyperbolically, which threatens to choke off the computational performance increases of chips that we have come to expect over time. We examine some of the quantitative implications of these trends by analyzing the International Technology Roadmap for Semiconductors. We compare the potential of replacing the global electronic interconnect of future chips with a photonic interconnect and see that there is in principle a four order of magnitude bandwidth-to-power ratio advantage for the latter. This indicates that it could be possible to dramatically improve chip performance without scaling transistors but rather utilize the capability of existing transistors much more efficiently. However, at this time it is not clear if these advantages can be realized. We discuss various issues related to the architecture and components necessary to implement on-chip photonic interconnect.

When using linear resistors to implement nanoelectronic resistor-logic demultiplexers, codes can be used to improve the voltage margins of these circuits. However, the resistors which have been fabricated in nanoscale crossbars are observed to be nonlinear in their current versus voltage (I-V) characteristics, showing an exponential dependence of current on voltage; we call these devices tunneling resistors. The introduction of nonlinearity can either improve or degrade the voltage margin of a demultiplexer circuit, depending on the particular code used. Therefore, the criterion for choosing codes must be redefined for demultiplexer circuits built from this type of nonlinear resistor. We show that for well-chosen codes, the nonlinearity of the resistors can be advantageous, producing a better voltage margin than can be achieved with linear resistors

Crossbar architectures are one approach to molecular electronic circuits for memory and logic applications. However, currently feasible manufacturing technologies for molecular electronics introduce numerous defects so insisting on defect-free crossbars would give unacceptably low yields. Instead, increasing the area of the crossbar provides enough redundancy to implement circuits in spite of the defects. We identify reliability thresholds in the ability of defective crossbars to implement boolean logic. These thresholds vary among different implementations of the same logical formula, allowing molecular circuit designers to trade-off reliability, circuit area, crossbar geometry and the computational complexity of locating functional components. We illustrate these choices for binary adders. For instance, one adder implementation yields functioning circuits 90% of the time with 30% defective crossbar junctions using an area only 1.8 times larger than the minimum required for a defect-free crossbar. We also describe an algorithm for locating a combination of functional junctions that can implement an adder circuit in a defective crossbar.

A nanoelectronic architecture is proposed that combines configurable, nanoscale diode crossbars with hysteretic resistor crossbars in order to implement general sequential circuits ("nano state machines"). The resulting circuits are inherently nonvolatile, require no static power dissipation, and are tolerant of variation in device characteristics. They are also unusual in that state information is stored using impedance encoding rather than voltage encoding. An example state machine, a two-bit counter, is modeled in SPICE and analyzed.

Current manufacturing of molecular electronics introduces defects, but circuits can be implemented by including redundant components. We identify reliability thresholds for implementing binary adders in the crossbar approach to molecular electronics. These thresholds vary among different implementations of the same logical formula, giving a tradeoff between yield and circuit area. For instance, one implementation has at least 90% yield with up to 30% defects for an area 1.8 times larger than the minimum required for a defect-free crossbar.

An architecture for nano-electronic computation based on crossbars of hysteretic resistors is presented. We show how such crossbars can implement inverting and non-inverting latches and sum-of-product logic functions, and give examples of a NAND gate, exclusive-OR gate, and half adder. Multiple hysteretic resistor crossbars may be combined to implement complex computational systems. The designs have been evaluated using SPICE (a general-purpose circuit simulation program), demonstrating the feasibility of implementation given a suitable nano-electronic substrate.

Configurable crossbars are the easiest computational structures to fabricate at the nanoscale. By creating multiple types of crossbars and assembling them into larger structures, we may implement general computation. Architectures for diode-based and transistor-based logic are presented, along with latching mechanisms. We present simulation results from defect-tolerance studies on two applications (a 3-bit adder and a 4-bit microprocessor) mapped onto defective, nanoelectronic fabrics, and outline strategies for fault tolerance.

Demultiplexers are expected to be key components in interfacing submicrometer-scale and nano-scale electronic circuits. Designing them is challenging because most nanoarchitectures are limited to simple regular structures, such as crossbars, and nanoelectronic circuits in general are likely to be plagued with relatively high hard-defect and soft-error rates. Previous work has shown how linear codes can be used to design defect-tolerant demultiplexers using resistor or diode crossbars. We extend those results with nonlinear codes, constructing resistor and diode crossbar-based demultiplexers that have better electrical characteristics and defect tolerance for a given area of the nano substrate, at the cost of more complex address encoding circuitry.

We present an approach to building defect-tolerant, nanoscale compute fabrics out of assemblies of defective crossbars of configurable FETs and switches. The simplest structure, the complementary/symmetry array, can implement AND-OR-INVERT functions, which are powerful enough to implement general computation. These arrays can be combined to create logic blocks capable of implementing sum-of-product functions, and still larger computations, such as state machines, can be obtained by adding additional routing blocks. We demonstrate the defect tolerance of such structures through experimental studies of the compilation of a small microprocessor onto a crossbar fabric with varying defect rates and compiler mapping parameters.

Accelerating a genetic algorithm (GA) by implementing it in a reconfigurable field programmable gate array (FPGA) is described. The implemented GA features: random parent selection, which conserves selection circuitry; a steady-state memory model, which conserves chip area; survival of fitter child chromosomes over their less-fit parent chromosomes, which promotes evolution. A net child chromosome generation rate of one per clock cycle is obtained by pipelining the parent selection, crossover, mutation, and fitness evaluation functions. Complex fitness functions can be further pipelined to maintain a high-speed clock cycle. Fitness functions with a pipeline initiation interval of greater than one can be plurally implemented to maintain a net evaluated-chromosome throughput of one per clock cycle. Two prototypes are described: The first prototype (c. 1996 technology) is a multiple-FPGA chip implementation, running at a 1 MHz clock rate, that solves a 94-row × 520-column set covering problem 2,200× faster than a 100 MHz workstation running the same algorithm in C. The second prototype (Xilinx XVC300) is a single-FPGA chip implementation, running at a 66 MHZ clock rate, that solves a 36-residue protein folding problem in a 2-d lattice 320× faster than a 366 MHz Pentium II. The current largest FPGA (Xilinx XCV3200E) has circuitry available for the implementation of 30 fitness function units which would yield an acceleration of 9,600× for the 36-residue protein folding problem.

The notion of quantum-dot cellular automata (QCA) as a possible replacement paradigm for conventional transistor-based logic is reviewed. Experiments using metal tunnel structures demonstrating a functional QCA cell are presented. It is shown that single electron tunnelling transistors used as electrometers verify proper switching of the QCA cell. Additionally, we provide evidence for a QCA cell switching frequency of 14 MHz, and a calculated upper limit of more than 5 GHz.

We present two implementations of the Cube-4 volume rendering architecture, developed at SUNY Stony Brook, on the Teramac custom computing machine. Cube-4 uses a slice-parallel ray-casting algorithm that allows for a parallel and pipelined implementation of ray-casting. Tri-linear interpolation, surface normal estimation from interpolated samples, shading, classification, and compositing are part of the rendering pipeline. Using the partitioning schemes introduced in this paper, Cube-4 is capable of rendering in real-time large datasets (e.g., 10243) with a limited number of rendering pipelines. Teramac is a hardware simulator developed at Hewlett-Packard Research Laboratories. Teramac belongs to the new class of custom computing machines, which combine the speed of special-purpose hardware with the flexibility of general-purpose computers. Using Teramac as a development tool, we implemented two working Cube-4 prototypes capable of rendering 1283 datasets in 0.65 s at a very low 0.96 MHz processing frequency. The results from these implementations indicate scalable performance with the number of rendering pipelines and real-time frame-rates for high-resolution datasets.

What is the best, near-term approach for building intelligent machines? We explore the impact of memristive memory on the technological and mathematical foundations of neuromorphic computing.

Convergent advances in neural modeling, neuroinformatics, neuromorphic engineering, materials science, and computer science will soon enable the development and manufacture of novel computer architectures, including those based on memristive technologies that seek to emulate biological brain structures. A new computational platform, Cog Ex Machina, is a flexible modeling tool that enables a variety of biological-scale neuromorphic algorithms to be implemented on heterogeneous processors, including both conventional and neuromorphic hardware. Cog Ex Machina is specifically designed to leverage the upcoming introduction of dense memristive memories close to computing cores. The MoNETA (Modular Neural Exploring Traveling Agent) model is comprised of such algorithms to generate complex behaviors based on functionalities that include perception, motivation, decision-making, and navigation. MoNETA is being developed with Cog Ex Machina to exploit new hardware devices and their capabilities as well as to demonstrate intelligent, autonomous behaviors in both virtual animats and robots. These innovations in hardware, software, and brain modeling will not only advance our understanding of how to build adaptive, simulated, or robotic agents, but will also create innovative technological applications with major impacts on general-purpose and high-performance computing.

Realizing adaptive brain functions subserving perception, cognition, and motor behavior on biological temporal and spatial scales remains out of reach for even the fastest computers. Newly introduced memristive hardware approaches open the opportunity to implement dense, low-power synaptic memories of up to 1015 bits per square centimeter. Memristors have the unique property of “remembering” the past history of their stimulation in their resistive state and do not require power to maintain their memory, making them ideal candidates to implement large arrays of plastic synapses supporting learning in neural models. Over the past decades, many learning rules have been proposed in the literature to explain how neural activity shapes synaptic connections to support adaptive behavior. To ensure an optimal implementation of a large variety of learning rules in hardware, some general and easily parameterized form of learning rule must be designed. This general form learning equation would allow instantiation of multiple learning rules through different parameterizations, without rewiring the hardware. This paper characterizes a subset of local learning rules amenable to implementation in memristive hardware. The analyzed rules belong to four broad classes: Hebb rule derivatives with various methods for gating learning and decay, Threshold rule variations including the covariance and BCM families, Input reconstruction-based learning rules, and Explicit temporal trace-based rules.

A neural modeling platform known as Cog ex Machina1 (Cog) developed in the context of the DARPA SyNAPSE2 program offers a computational environment that promises, in a foreseeable future, the creation of adaptive whole-brain systems subserving complex behavioral functions in virtual and robotic agents. Cog is designed to operate on low-powered, extremely storage-dense memristive hardware3 that would support massively-parallel, scalable computations. We report an adaptive robotic agent, ViGuAR4, that we developed as a neural model implemented on the Cog platform. The neuromorphic architecture of the ViGuAR brain is designed to support visually-guided navigation and learning, which in combination with the path-planning, memory-driven navigation agent - MoNETA5 - also developed at the Neuromorphics Lab at Boston University, should effectively account for a wide range of key features in rodents' navigational behavior.

We present an experimental demonstration of a latch in a clocked quantum-dot cellular automata (QCA) device. The device consists of three floating micron-size metal dots, connected in series by multiple tunnel junctions and controlled by capacitively coupled gates. The middle dot acts as an adjustable barrier to control single-electron tunneling between end dots. The position of a switching electron in the half cell is detected by a single-electron electrometer. We demonstrate “latching” of a single electron in the end dots controlled by the gate connected to the middle dot. This ability to lock an electron in a controllable way enables pipelining, power gain and reduced power dissipation in QCA arrays.

The instar and outstar synaptic models are among the oldest and most useful in the field of neural networks. In this paper we show how to approximate the behavior of instar and outstar synapses in neuromorphic electronic systems using memristive nanodevices and spiking neurons. Memristive nanodevices are especially attractive for this application since such devices are tiny, can be densely packed in crossbar-like structures and possess the long time constants, or memory, needed by the synaptic models.

The DARPA Systems of Neuromorphic Adaptive Plastic Scalable Electronics (SyNAPSE) initiative aims to create a new generation of high-density, low-power consumption chips capable of replicating adaptive and intelligent behavior observed in animals. To ensure fast speed, low power consumption, and parallel learning in billions of synapses, the learning laws that govern the adaptive behavior must be implemented in hardware. Over the past decades, multitudes of learning laws have been proposed in the literature to explain how neural activity shapes synaptic connections to support adaptive behavior. In order to implement as many of these laws as possible on the hardware, some general and easily parameterized form of learning law has to be designed and implemented on the chip. Such a general form would allow instantiation of multiple learning laws through different parameterizations without rewiring the hardware. From the perspectives of usefulness, stability, homeostatic properties, and spatial and temporal locality, this project analyzes four categories of existing learning rules: 1. Hebb rule derivatives with various methods for gating learning and decay; 2. Threshold rule variations including the covariance and BCM families; 3. Error-based learning rules; and 4. Reinforcement rules For each individual category a general form that can be implemented in hardware was derived. Even more general forms that include multiple categories are further suggested.

The neuromorphic paradigm is attractive for nanoscale computation because of its massive parallelism, potential scalability, and inherent defect-, fault-, and failure-tolerance. We show how to implement timing-based learning laws, such as spike-timing-dependent plasticity (STDP), in simple, memristive nanodevices, such as those constructed from certain metal oxides. Such nano-scale ldquosynapsesrdquo can be combined with CMOS ldquoneuronsrdquo to create neuromorphic hardware several orders of magnitude denser than is possible in conventional CMOS. The key ideas are: (1) to factor out two synaptic state variables to pre- and post-synaptic neurons; and (2) to separate computational communication from learning by time-division multiplexing of pulse-width-modulated signals through synapses. This approach offers the advantages of: better control over power dissipation; fewer constraints on the design of memristive materials used for nanoscale synapses; learning dynamics can be dynamically turned on or off (e.g. by attentional priming mechanisms communicated extra-synaptically); greater control over the precise form and timing of the STDP equations; the ability to implement a variety of other learning laws besides STDP; better circuit diversity since the approach allows different learning laws to be implemented in different areas of a single chip using the same memristive material for all synapses.

High-performance random number generators (RNGs) can be economically implemented in popular field programmable gate arrays without the need for arithmetic circuitry by employing cellular automata (CA) with a neighborhood size of four and an asymmetrical, non-local neighborhood connection scheme. Each cell (i.e., RNG bit) requires only a single 4-input lookup table and a single flip-flop. From each of various 1-d, 2-d, and 3-d networks with periodic boundary conditions, the 1000 highest entropy CA RNGs were selected from the set of 65,536 possible uniform (all CA truth tables the same) implementations. Each set of 1000 high-entropy CA was then submitted to Marsaglia's DIEHARD suite of random number tests. A number of 64-bit, neighbor-of-four CA-based RNGs have been discovered that pass all tests in DIEHARD without resorting to either site spacing or time spacing to improve the RNG quality.

The Plasma chip, designed specifically to address issues important to custom computing machines (CCM), completes a 100% fully automatic place and route in approximately three seconds. Plasma FPGAs using 0.8 micron CMOS are packaged in large multichip modules (MCMs). Plasma introduces some innovative architecture concepts including hardware support for large multiported register files.

Teramac is a large custom computer which works correctly despite the fact that three quarters of its FPGAs contain defects. This is accomplished through unprecedented use of defect tolerance, which substantially reduces Teramac's cost and permits it to have an unusually complex interconnection network. Teramac tolerates defective resources, like gates and wires, that are introduced during the manufacture of its FPGAs and other components, and during assembly of the system. We have developed methods to precisely locate defects. User designs are mapped onto the system by a completely automated process that avoids the defects and hides the defect tolerance from the user. Defective components are not physically removed from the system.

Random number generators (RNGs) based upon neighborhood-of-four cellular automata (CA) with asymmetrical, non-local connections are explored. A number of RNGs that pass Marsaglia's rigorous Diehard suite of random number tests have been discovered. A neighborhood size of four allows a single CA cell to be implemented with a four-input lookup table and a one-bit register which are common building blocks in popular field programmable gate arrays (FPGAs). The investigated networks all had periodic (wrap around) boundary conditions with either 1-d, 2-d, or 3-d interconnection topologies. Trial designs of 64-bit networks using a Xilinx XCV1000-6 FPGA predict a maximum clock rate of 214 MHz to 230 MHz depending upon interconnection topology.

Prototypes are invaluable for studying special purpose parallel architectures and custom computing. This paper describes a new FPGA, called Plasma- the heart of a configurable custom computing engine (Teramac) that can execute synchronous logic designs up to one million gates at rates up to one megahertz. Plasma FPGA's using 0.8 micron CMOS are packaged in large multichip modules (MCMs). A large custom circuit may be mapped onto the hardware in approximately two hours, without user intervention. Plasma introduces some innovative architecture concepts including hardware support for large multiported register files.

The Teramac configurable hardware system can execute synchronous logic designs of up to one million gates at rates up to 1 megahertz. A fully configured Teramac includes half a gigabyte of RAM and hardware support for large multiported register files. The system has been built from custom FPGA's packaged in large multichip modules (MCMs). A large custom circuit (/spl sim/1,000,000 gates) may be compiled onto the hardware in approximately 2 hours, without user intervention. The system is being used to explore the potential of custom computing machinery (CCM).

The difficulty in creating a configurable machine lies in providing enough wires that placement and routing can be done with no human intervention. Several researchers have previously used tens of FPGAs to create configurable custom machines [8–11]; Teramac allows experiments using many hundreds of FPGAs by providing a routing-rich environment for implementing user designs by using custom FPGAs, MCM's and PC boards.

The primary goal of a Modular Neural Exploring Traveling Agent (MoNETA) project is to create an autonomous agent capable of object recognition and localization, navigation, and planning in virtual and real environments. Major components of the system perform sensory object recognition, motivation and rewards processing, goal selection, allocentric representation of the world, spatial planning, and motor execution. MoNETA is based on the real time, massively parallel, Cog Ex Machina environment co-developed by Hewlett-Packard Laboratories and the Neuromorphics Lab at Boston University. The agent is tested in virtual environments replicating neurophysiological and psychological experiments with real rats. The currently used environment replicates the Morris water maze [1]. The motivational system represents the internal state of the agent that can be adjusted by sensory inputs. In the Morris water maze, only one drive can be satisfied (a desire to get out of the water) that persists as long as the animat is swimming and sharply decreases as soon as it is fully positioned on the platform. Another drive – curiosity – is constantly active and is never satisfied. It forces the agent to explore unfamiliar parts of the environment. Familiarity with environmental locations provides inhibition to the curiosity drive in a selective manner, so that recently explored locations are less appealing than either unexplored locations or locations that were explored long time ago. The main output of the motivational system is a goal selection map. It is based on competition between goals set by the curiosity system and goals learned by the animat. The goal selection map uses a winner-take-all selection of the most prominent input signal as a winning goal. Because curiosity-driven goals receive weaker inputs than well-learned reward locations, they can only win if there are no prominent inputs corresponding to the learned goals with an active motivational drive. The spatial planning system is built around a previously developed neural algorithm for goal-directed navigation [2]. The original model provided the desired destination and left it up to the virtual environment to move the animat in this location. In MoNETA the model was extended by a chain of neural populations that convert the allocentric desired destination into an allocentric desired direction and further into a rotational velocity motor command. A second extension of the model deals with the mapping of the environment. The original algorithm included goal and obstacle information into path planning, but this information was provided in the form of allocentric maps where the locations of both the goals and obstacles were received directly from the environment. MoNETA uses these maps, but also creates them from egocentric sensory information through a process of active exploration. Although the current version only uses somatosensory information, visual input will be added in later stages. The system converts egocentric representations to allocentric ones and then learns the mapping of obstacles and goals in the environment. It uses a learning rule that is local to dendrites and does not require any postsynaptic activity. The complete implementation of MoNETA consists of 75,301 neurons and 1,362,705 synapses.

All death certificates with amyotrophic lateral sclerosis (ALS) or motor neuron disease (MND) as the primary or underlying cause occurring among Kentucky residents between 1964 and 1984 were manually reviewed. Geographic variability within Kentucky was evident for three intervals, 1964-1967, 1968-1978, and 1979-1984, with a more marked pattern among females than among males. There was a shifting age pattern of MND mortality with a higher proportion of cases in older ages for the most recent time period. Again, this pattern was more marked among females. Furthermore, there was a slight increase in total average annual age adjusted ALS/MND mortality rates over the three intervals. The increase is slight, but with the previous stability of reported rates and the shifting geographic and age patterns, there is evidence to support the need for incidence studies targeted at specific environmental exposures.