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Next generation automotive radar sensors are increasingly becoming sensitive to cost and size, which will leverage monolithically integrated Radar System-on-Chips (RadarSoC). This paper presents a 76–81 GHz RadarSoC as an evaluation vehicle for an automotive 22nm fully-depleted silicon-over-insulator (FD-SOI) CMOS technology. It features a digitally controlled oscillator, two millimeter wave transmit channels and receive channels, an analog base-band with analog-to-digital conversion as well as a digital signal processing unit with on-chip memory.

This paper presents a 190-GHz direct-conversion receiver capable of supporting higher order modulation schemes and implemented in a 130-nm SiGe BiCMOS technology. The circuit consists of a low-noise amplifier, an active fundamental mixer, a local-oscillator driver, a variable-gain baseband (BB) amplifier, and a totem-pole output stage. To exploit the advantages of sub-THz frequencies in terms of available bandwidth (BW) at a low dc power consumption, all circuit blocks are concurrently optimized for large BW and high power efficiency. A high and tunable conversion gain as well as a large maximum BB voltage swing is targeted to allow direct operation with state-of-the-art analog-to-digital converters. While consuming only 122 mW of dc power, the fabricated circuit exhibits a record 3-dB RF BW of 35 GHz, a maximum conversion gain of 47 dB with a tuning range of 20 dB, a maximum BB voltage swing of more than 800 $\text {mV}_{\mathrm{ pp}}$ , and a minimum double-sideband noise figure of 10.7 dB.

In this paper we review high-speed radio-frequency integrated circuits operating up to 210 GHz and present selected state-of-the-art circuits with leading-edge performance, which we have designed at our chair. The following components are discussed employing bipolar complementary metal oxide semiconductors (BiCMOS) technologies: a 200 GHz amplifier with 17 dB gain and around 9 dB noise figure consuming only 18 mW, a 200 GHz down mixer with 5.5 dB conversion gain and 40 mW power consumption, a 190 GHz receiver with 47 dB conversion gain and 11 dB noise figure and a 60 GHz power amplifier with 24.5 dBm output power and 12.9 % power added efficiency (PAE). Moreover, we report on a single-core flash CMOS analogue-to-digital converter (ADC) with 3 bit resolution and a speed of 24 GS/s. Finally, we discuss a 60 GHz on-off keying (OOK) BiCMOS transceiver chip set. The wireless transmission of data with 5 Gb/s at 42 cm distance between transmitter and receiver was verified by experiments. The complete transceiver consumes 396 mW.

This paper presents the design and characterization of a 24-GS/s 3-bit single-core flash analog-to-digital converter (ADC) in 28-nm low-power digital CMOS. It shows the design study of the track-and-hold circuit and subsequent buffer stage and provides equations for bandwidth calculations without extensive circuit simulations. These results are used to target leading-edge speed performance for a single ADC core. The ADC is capable of achieving its full sampling rate without time interleaving, which makes it the fastest single-core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 0.4 W and an effective number of bits of 2.2 at 24 GS/s, the ADC achieves a figure of merit of 3.6 pJ per conversion step while occupying an active area of ${\hbox{0.12 mm}}^{2}$ . Due to its high sampling frequency this ADC can enable ultra-high-speed ADC systems when combined with moderate time interleaving.

This paper presents the design of a 60-GHz low-noise amplifier (LNA) in a 28-nm low-power (LP) bulk CMOS process. As the technology is optimized for digital LP applications, the design of millimeter-wave (mm-wave) circuits requires high-frequency design and modeling of all active and passive devices. This includes the development of a suitable RF-transistor layout, as well as transmission lines and high- $Q$ capacitors. The mm-wave circuit design aspects are further discussed with considerations about possible dc-distribution approaches, broadband matching networks, and optimum transistor loads. The proposed approach and device models have been validated with the fabrication and characterization of a two-stage 60-GHz LNA. This circuit exhibits 13.8 dB of power gain, 18 GHz of bandwidth, 4 dB of minimum noise figure, and an input referred 1-dB compression point at $-$ 12.5 dBm consuming 24 mW of dc power. Based on this performance and to the authors’ best knowledge, the presented amplifier shows the highest reported value for a commonly used figure-of-merit of 60-GHz LNAs.

This letter presents a distributed amplifier fabricated in a 0.13- $\mu$ m SiGe BiCMOS technology for applications with large bandwidth requirements. The main design goals of large bandwidth and high gain are achieved by cascading three bandwidth-optimized traveling-wave amplifier stages. The termination resistance variations, which have large influence on the gain, are compensated by implementing electrically trimmable resistors. Measurements of the amplifier trimmed for optimum gain flatness show a gain of 18.7 dB over a 3-dB bandwidth of 180 GHz. To the authors' best knowledge, the resulting gain-bandwidth product of 1.6 THz is the highest reported to date.

This letter presents an active 200 GHz fundamental down-conversion mixer based on the Micromixer topology for low-power high data-rate wireless communications. The mixer-core operation requires a $-$ 5 dBm LO-signal, which is generated on-chip from an external single-ended source of only $-$ 20 dBm by means of a power-efficient LO-driver and a passive balun. Mixer, LO-driver and balun have been implemented together in a 450 GHz SiGe BiCMOS technology occupying a circuit core area of 0.21 mm $^{2}$ . For a 200 GHz LO-signal, the characterized circuit exhibits a maximum conversion gain of 5.5 dB over a 3 dB RF-bandwidth of 30 GHz, requiring only 17.4 and 22.5 mW of DC-power in the mixer core and in the LO-driver, respectively.

The design, analysis, modelling and measurement of transmission lines with very low characteristic impedance in 28 nm bulk CMOS is presented. The so-called zero-Ohm lines are very well suited for power distribution networks and AC shorts in millimetre-wave circuits because of their accurate modelling up to extremely high frequencies and because they do not require metal–insulator–metal capacitors, which are usually not available in digital CMOS processes. Instead, they rely on simple metal structures, which can optionally be enhanced by integrating MOS capacitors. Applying transmission line theory, the lines can be described with models, which are scalable in length and width. Implemented test structures demonstrate a compact line of 450 μm length, which transforms an open circuit to an impedance close to 0 Ω for frequencies above 1 GHz.

In this paper a 6th order bandpass intermediate filter with a 10% settling time of 70 ns is presented. The filter is optimized to provide a short settling time for operation in a pulsed wake-up receiver. To the best of our knowledge, the presented work provides the fastest turn-on time among comparable designs. Such a fast turn-on behavior is very beneficial for recent wake-up radios as it enables further reduction in the power dissipations of receiver circuits. At a center frequency of 70MHz the measured −3-dB bandwidth of the filter is less than 25 MHz. The center frequency can be tuned by ±5% as well, to compensate the effect of the mismatch. The circuit is based on the multi-feedback structure and exhibits a peak gain of 4 dB at its pass band. While the required current for operation is 1.65 mA, the in-band 3rd order intermodulation intercept point is −5 dB. It is implemented in IHP 130nm CMOS process and can be operated from a 2–3V supply.

This paper describes the design, implementation and characterization of a dualband medium-power amplifier. The circuit consists of three cascaded cascode stages. With the aim of maximizing the overall amplifier bandwidth, the inter-stage matching networks are designed for operation in two adjacent bands. Shielded microstrips and zero-Ohm transmission lines were used to ensure precise matching. The amplifier provides a power gain of 23.7 dB at 180 GHz with a 3 dB bandwidth of 17.2 GHz and a power gain of 20.2 dB at 205 GHz with a 3 dB bandwidth of more than 22.8 GHz. The maximum output power at 1 dB gain compression is 2.2 dBm at 170 GHz while the maximum measured output power is 3.6dBm at 180 GHz. The circuit requires 24mA from a 2.5V supply source and has been fabricated on 0.4mm2 of a 130nm SiGe BiCMOS technology.

This paper describes the design, modelling and characterization of transmission lines for millimetre wave silicon integrated circuits up to 65 GHz. The simulation results of three different EM simulators for a selected hybrid coplanar layout structure are presented. Two different deembedding methods are investigated and compared with respect to sensitivity to typical measurement errors. Finally both methods are applied to the measurement results of the fabricated test structures in a 250 nm BiCMOS technology showing good agreement to EM simulations and predicted sensitivity to measurement errors.

Enabling the vast computational and throughput requirements of future high performance computer systems and data centers requires innovative approaches. In this paper, we will focus on the communication between computer boards. One alternative to the bottleneck presented by copper wire based cable-bound communication is the deployment of wireless links between nodes consisting of processors and memory on different boards in a system. In this paper, we present an interdisciplinary approach that targets an integrated wireless transceiver for short-range ultra-high speed computer board-to-board communication. Based on our achieved results and current developments, we will also estimate energy consumption of such a transceiver.

This paper presents the design and characterization of a 24 GS/s, 3 bit flash ADC in 28nm low-power (LP) digital CMOS. The circuit was designed with the goal of achieving speed performance above state of the art for a single ADC core. The ADC is capable of delivering its full sampling rate without time interleaving, which makes it the fastest single core ADC in CMOS reported to date to the best of our knowledge. With a power consumption of 406mW and an effective number of bits (ENOB) of 2.2 at 24 GS/s, the ADC achieves a figure of merit (FOM) of 3.6 pJ per conversion step, which is the lowest reported value for single-core ADCs operating above 15 GHz. The very high sampling rate of the presented ADC enables ultra-high-speed ADC systems through moderate time interleaving.

This paper presents a method to increase the input bandwidth of switched capacitor (SC) track and hold amplifiers (THAs), which is particularly suitable for time-interleaved analog-to-digital converters (ADCs). With a simple model for the track and hold stage, it is shown that frequency compensation techniques at the input of the THA can substantially increase the bandwidth at the controlled cost of increased distortion. A design example shows a bandwidth increase of 60% for a THA in a 4-bit ADC.

This paper presents the design and characterization of a 10 GS/s track and hold amplifier (THA). The circuit was fabricated in a 28 nm CMOS technology. It is based on a switched capacitor approach. At a sampling rate of 10 GS/s, the total harmonic distortion is -38dBc with a 3.75 GHz input signal. The chip includes an active balun and buffer stages for the clock signal and consumes 50 mW, which is significantly lower than the state-of-the-art at similar performance. It can work with maximum peak-to-peak differential input voltages of up to 800 mV, which is the highest reported for high-speed CMOS implementations and comparable with the performance of state-of-the-art bipolar implementations.

An overview about research activities in the field of high frequency integrated circuits and communication systems performed within the German cluster project Cool Silicon is given. Cool Silicon is located around Dresden/Silicon Saxony/Germany and features around 50 projects and 100 partners from industry and research institutions, and aims at significantly increasing the energy efficiency of information and communications technologies.

An overview about the German cluster project Cool Silicon aiming at increasing the energy efficiency for semiconductors, communications, sensors and software is presented. Examples for achievements are: 1000 times reduced gate leakage in transistors using high-fc (HKMG) materials compared to conventional poly-gate (SiON) devices at the same technology node; 700 V transistors integrated in standard 0.35 µm CMOS; solar cell efficiencies above 19% at < 200 W/m2 irradiation; 0.99 power factor, 87% efficiency and 0.088 distortion factor for dc supplies; 1 ns synchronization resolution via Ethernet; database accelerators allowing 85% energy savings for servers; adaptive software yielding energy reduction of 73% for e-Commerce applications; processors and corresponding data links with 40% and 70% energy savings, respectively, by adaption of clock frequency and supply voltage in less than 20 ns; clock generator chip with tunable frequency from 83-666 MHz and 0.62-1.6 mW dc po wer; 90 Gb/s on-chip link over 6 mm and efficiency of 174 fJ/mm; dynamic biasing system doubling efficiency in power amplifiers; 60 GHz BiCMOS frontends with dc power to bandwidth ratio of 0.17 mW/MHz; driver assistance systems reducing energy consumption by 10% in cars.