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Composite materials and especially those made from pre-impregnated (prepreg) material are widely used in the aerospace industry. To achieve the tight assembly dimensional tolerances required, manufacturers rely on additional manufacturing steps like shimming or machining, which generate extra waste, which are time-consuming and expensive. Prepreg sheets come naturally with fiber and resin volume content variability that leads manufacturers to guarantee cured ply thicknesses within a typical +/−5% margin of their nominal values. For thick laminates, this can equate to a thickness variability of as much as a few millimeter. To solve the issue, it is proposed to twin in situ laser measurements of the uncured prepreg thickness with numerical simulations of the laminate autoclave consolidation and cure process and to adjust the number of additional sacrificial plies in the laminate based on the model predictions. This reduces the need for expensive and time-consuming trial and error approaches, extra machining operations, and results in the production of a part with high accuracy dimensions. Data for IM7/8552 and IM7/977-3 are presented to demonstrate the potential of the method to reach an almost exact target thickness for flat panels.

Introduction: Evidence-based teaching and learning strategies should underpin any educational activity. This is particularly important for interprofessional education (IPE) activities, where there is an expectation that healthcare professions are taught using best available evidence. There is a research–practice gap that this review aims to address by using the current evidence to develop recommendations regarding optimal design components to better inform faculty who design IPE. Methods: A five-stage scoping review was conducted. Methodological characteristics and IPE design components of primary and review studies were extracted. Three important components of design—participants (level and stage of progression, discipline type and number, group size and ratios), learning constructs (theories, frameworks, learning objectives) and learning approaches (exchange, observation, action, simulation and practice)—were reviewed to develop recommendations regarding effective design. Results: A total of 41 papers were eligible for inclusion, 24 primary and 17 review studies. The primary studies were predominantly descriptive case studies with 31 disciplines involved in IPE activities across the studies. There was inconsistent reporting of learning constructs utilised in design, and the most reported learning approach was exchange. There was significant variability in the aims and design of the 17 review studies, ranging from systematic reviews to realist reviews, with the number of included studies ranging from six to 104. Conclusions: There was a lack of detailed reporting regarding design components, which limits the evidence base to inform IPE design. Reported components from the primary studies were augmented by findings from the review studies and the wider literature, which enabled the development of recommendations to assist faculty in the design of IPE programs and activities.

Introduction Implementation of interprofessional education (IPE) is recognised as challenging, and well-designed programs can have differing levels of success depending on implementation quality. The aim of this review was to summarise the evidence for implementation of IPE, and identify challenges and key lessons to guide faculty in IPE implementation. Methods Five stage scoping review of methodological characteristics, implementation components, challenges and key lessons in primary studies in IPE. Thematic analysis using a framework of micro (teaching), meso (institutional), and macro (systemic) level education factors was used to synthesise challenges and key lessons. Results Twenty-seven primary studies were included in this review. Studies were predominantly descriptive in design and implementation components inconsistently reported. IPE was mostly integrated into curricula, optional, involved group learning, and used combinations of interactive and didactic approaches. Micro level implementation factors (socialisation issues, learning context, and faculty development), meso level implementation factors (leadership and resources, administrative processes), and macro level implementation factors (education system, government policies, social and cultural values) were extrapolated. Sustainability was identified as an additional factor in IPE implementation. Conclusion Lack of complete detailed reporting limits evidence of IPE implementation, however, this review highlighted challenges and yielded key lessons to guide faculty in the implementation of IPE.

This paper proposes a power-efficient and memory-optimized FPGA-based solution for the memory and compute-intense re-gridding process used in implementing Non-uniform Fast Fourier Transform (NuFFT) algorithm. Re-gridding refers to mapping non-equispaced sampled data onto a uniform grid using an interpolation kernel function. Re-gridding is the most time-consuming step in the entire NuFFT computation. The proposed solution is based on better utilization of FPGA resources and minimizing the number of accesses to the external memory. We demonstrate high performance over a wide range of configurations and data-sizes. This paper targets a generic solution to arbitrary sampling trajectories and gives trajectory specific solutions for some well-known trajectories in NuFFT applications, such as magnetic resonance imaging and synthetic aperture radar. Compared with existing solutions, throughput is improved by over 9.6 when compared with the existing FPGA-based techniques, whereas computational power efficiency (in terms of MFLOPS/Watt) is improved by over 15 times. Compared with GPU-based technique, 9.59 times higher MFLOPS per watts are achieved. The proposed architecture is implemented using hardware description language as well as high-level synthesis (HLS)-based OpenCL framework and the comparison is reported. Hence, this paper also serves as a reference for the comparison of HLS-based solutions against optimized HDLs. Accuracy of the re-gridding process is also reported in terms of signal-to-noise ratio.

Magnetic Resonance Imaging (MRI) is widely used in medical diagnostics. Sampling of MRI data on Cartesian grids allows efficient computation of the Inverse Discrete Fourier Transform for image reconstruction using the Inverse Fast Fourier Transform (IFFT) algorithm. Though the use of Cartesian trajectories simplifies the IFFT computation, non-Cartesian trajectories have been shown to provide better image resolution with lower scan times. To improve the processing time of MRI image reconstruction for these optimized non-Cartesian trajectories using a Non-uniform Fast Fourier Transform (NuFFT) algorithm, dedicated accelerators are required. We present an FPGA-based MRI solution to implement NuFFT for image reconstruction. The solution is based on the design of an efficient custom accelerator on FPGA using OpenCL, and covers all the phases necessary to reconstruct an image with high accuracy, starting from raw scan data. The architecture can be easily extendable to tackle 3D imaging, and k-space properties have been analyzed to reduce the number of samples processed, achieving satisfactory reconstruction accuracy while positively impacting processing time. Our solution achieves a marked improvement over previously published FPGA- and CPU-based implementations and, due to its scalability, it is suitable for the image sizes common in MRI acquisitions.

This paper proposes an efficient architecture (InvArch) for computing matrix inversion using Gauss-Jordan Elimination method. The proposed architecture exploits parallelism through pipelined floating-point computational units and reduces the number of floating-point multiplication units required compared with the existing pipelined implementations. The reduction in multiplication units results in over 80% reduction in hardware for floating point computation units. The architecture performs in-place inversion and provides scalability across the rows and columns. Hardware efficiency is achieved by reaping benefit from regularity in computation and better utilization of pipelined computational resources. Multiple rows are normalized within an iteration of Gauss-Jordan algorithm that allows reduction in number of floating-point multiplication units in the elimination step. In addition to implementing the architecture, an analytical performance model is also developed for InvArch and some related works. InvArch achieves performance comparable to reference architectures in terms of clock cycles and throughput while using significantly less hardware resources.

Range Migration Algorithm (RMA) is one of the most practiced frequency domain based algorithms for Synthetic Aperture Radar (SAR) image reconstruction. While computationally more intensive than Polar Format Algorithm (PFA), it has superior image reconstruction for large squint angles. Due to the real-time nature of SAR imaging-related tasks, it is desired to have faster hardware implementations of reconstruction algorithms. In this paper we study FPGA-based implementation of the RMA algorithm using a novel pipelined Non-uniform FFT (NuFFT) module that optimizes its operation by exploiting the order in which samples are presented. We demonstrate that we can achieve processing speed of over 600 Msps (Mega Samples per Second) for the implemented RMA algorithm using the FPGA.

We propose MedianPipes, a novel, FPGA based, highly pipelined and scalable architecture for median filtering. Median filters and its variants are widely used for noise suppression in image processing. All variants of median filter depend on the computation of median values. MedianPipe is a highly pipelined architecture and hence an ideal fit for FPGAs. It does not make any assumptions about the image to fit on the on-chip memory. Instead, the image is assumed to be streamed-in in the form of image slices. Multiple MedianPipe modules are used depending on the size of image slice and hence the overall hardware complexity of proposed technique scales linearly with image-slice size. The architecture for MedianPipe is based on the principle of merge sort and uses a median window of size 3 x 3. It consists of two stepped sorting process: The first step is to sort the pixels within each row of median window to get sorted rows. This sorting is done using a single comparator over multiple clock cycles. The sorted rows are saved in block memory based First-In-First-Out (FIFO) memory and reused to calculate the medians corresponding to three median windows. The second step is to merge these sorted rows to find the median using a merger block. The merger block consists of three comparators and read out a single value every cycle once the pipeline is filled. Without loss of generality, the pixels of an image slice are assumed to be read in a column major format. All the median values within the column of the image slice can be computed in parallel using multiple MedianPipes. The computation of median values in the following column is delayed by a clock cycle. Hardware resources scale linearly by varying the pixel sizes and number of MedianPipes. The pixel rate achieved for various pixel sizes is well above 124 MHz which is the standard for 1080p High-Definition.

A small, fine-grained systolic FFT architecture is described that is fast, programmable, can do non-power-of-two DFTs, and provides a higher signal-to-noise ratio for a given fixed-point word length than traditional block floating point approaches. To demonstrate the basic architecture, several designs were implemented using 65nm FPGA technology: (1) fixed-size 256-point and 1024-point circuits; (2) a power-of-two variable FFT circuit for LTE OFDM; and (3) a non-power-of-two circuit for LTE SC-FDMA DFT computations, that is programmed by entering parameter values into a single ROM memory. These three circuits demonstrate >37%, 62% and >100% higher throughputs than the other pipelined and memory-based FFTs to which they are compared. These circuits run at clocks speeds as high as 566 MHz, 46% higher than any other circuit in the comparisons. Finally, the architecture provides scalable throughput by increasing the array size.

Many Hughes tactical and strategic programs need high performance image processing. For example, photo-interpretation applications can require up to four orders of magnitude speedup over conventional computer architectures. Therefore, parallel processing systems are needed to help close the processing gap. Vision applications can usually be decomposed into three levels of processing called high, intermediate, and low level vision. Each processing level typically requires different types of numeric/symbolic computation, processing task granularities, and communications bandwidths. No parallel processing system is commercially available that is optimized for the entire range of computations. To meet these processing challenges, the image understanding architecture (IUA) has been developed by Hughes in collaboration with the University of Massachusetts. The IUA is a heterogeneous, hierarchical, associative parallel processor that is organized in three levels corresponding to the vision problem. Its lowest level consists of a large content addressable array parallel processor. This array of 'per pixel' bit serial processors is used for fixed point, low level numeric, and symbolic computations. The middle level is an interface communications array processor (ICAP). ICAP is an array of digital signal processing chips from TI TMS320Cx line, used for high speed number crunching. The highest level is the symbolic processing array. It is an array of general purpose microprocessors in which the artificial intelligence content of the image understanding software resides. A set of benchmarks from the DARPA/ORD sponsored SCORPIUS program were developed using the IUA. The set of algorithms included low level image processing as well as high level matching algorithms. Benchmark performance on the second generation IUA hardware is over four orders of magnitude faster than equivalent algorithms implemented on a DEC VAX 8650. The first generation hardware is operational. Development of the second generation hardware and software for DARPA's Unmanned Ground Vehicle Program is under way in collaboration with the University of Massachusetts and Amerinex Artificial Intelligence.© (1992) COPYRIGHT SPIE--The International Society for Optical Engineering. Downloading of the abstract is permitted for personal use only.