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5. Dual-Gate JFET Modeling II: Source Pinchoff Voltage and Complete I\textrm {ds} Modeling Formalism.

Author

Xia, Kejun, McAndrew, Colin C., and Grote, Bernhard

Subjects
LOGIC circuits, FIELD-effect transistors, TUNNEL junction devices, COMPUTER simulation, ELECTRONIC linearization
Abstract

This paper studies the phase diagram of source pinchoff of dual-gate JFETs and presents a source pinchoff modeling formalism that is smooth across the phase boundaries. Based on this, an I\textrm {ds} model is derived, which is numerically robust for any value of top- and bottom-gate voltages. The method is applied to both the exact model for I\textrm {ds} and an approximated form based on mid-point-potential linearization, and is verified by comparison with numerical simulation. Modeling of short-channel effects is included. [ABSTRACT FROM AUTHOR]

Published
2016
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