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This letter presents a design, fabrication, and measurement of a ring-resonator-based subterahertz (sub-THz) dielectric sensor. The sensor consists of a ring-resonator-based notch filter, a sub-THz dielectric waveguide (DWG), and a pair of transitions from the microstrip line to the DWG. With low-loss and high permittivity silicon, the detected relative permittivity for materials is at the range of 1-11.9.

In this paper, an adaptive N-path filter design technique is presented. The filter designed by this method can be reconfigured to different shapes, e.g., Butterworth or Chebyshev with variable bandwidth (BW), based on the user requirements. In addition, an analytical synthesis procedure is introduced to realize high-order bandpass filters (BPFs) based on N-path architecture with a prescribed set of specifications. A proof-of-concept BPF is fabricated and measured in a 65-nm CMOS process. The filter can be reconfigured to realize different filter shapes by changing coupling capacitors. The BW of the proposed filter is also tunable. The passband of the filter is tunable from 0.2 to 1.2 GHz with a gain of 14.5-18 dB, a noise figure of 3.7-5.5 dB, and a total power consumption of 37.5-52.7 mW. The channel BW can be varied from 20 to 40 MHz and the filter out-of-band third-order intercept point (Δ f=50 MHz) is 25 dBm.

This paper presents for the first time the design, fabrication, and demonstration of a dielectric waveguide (DWG)-based ortho-mode sub-THz interconnect channel for planar chip-to-chip communications. By combining the proposed new transition of microstrip line with DWG orthogonally, the ortho-mode transition is constructed to form an ortho-mode channel. The measured minimum insertion losses for the Ey11 mode and the Ex11 mode are 6.6 dB with 20.3-GHz 3-dB bandwidth and 6.5 dB with 55.2-GHz 3-dB bandwidth, respectively. The simulation and measurement results agree well with each other.

This paper presents a dielectric waveguide based multi-mode sub-THz interconnect channel for high data-rate high bandwidth-density planar chip-to-chip communications. By using a proposed new transition of microstrip line to dielectric waveguide, the interconnect channel achieves wide bandwidth on two orthogonal modes Ey11 and Ex11. To the authors' knowledge, this is the first demonstration of a multi-mode sub-THz interconnect channel. The measured minimum insertion losses for mode Ey11 and mode Ex11 are 8.0 dB with 21.3 GHz 3-dB bandwidth and 9.0 dB with 24.0 GHz 3-dB bandwidth, respectively.

This paper presents a high energy-efficiency and high bandwidth-density dielectric waveguide based sub-THz interconnect. A bumpless flip-channel packaged nearfield coupled transition based channel together with the holistic active circuit design scheme boosts the energy efficiency to the record based on the authors' best knowledge. The channel demonstrates the transmission loss of 0.04 dB/mm and the bending loss of 0.17 dB/bend. This proof-of-concept sub-THz link, with active circuits in 65 nm bulk CMOS, demonstrates the bit error rate of less than 1 × 10-12 up to 12.1 Gb/s with a high bandwidth density of 80.7 Gb/s/mm2. The record energy efficiency of 0.32 pJ/b is achieved at 10 Gb/s with 3.2 mW power consumption. The communication distance is 46.2 mm.

This paper presents a tunable active bandpass filter (BPF) with adjustable transmission zeros (TZs) close to the passband for software-defined radio (SDR) applications. The RF front-end frequency selectivity is enhanced by the creation of TZs that also improve the out-of-band (OOB) input-referred third-order intercept point (IIP3). The filter is based on two-path signal cancellation and consists of a tunable BPF in parallel with two tunable bandstop filters. This combination ensures the correct amplitude and phase relationships across a wide tuning range to create adjustable TZs without sacrificing the gain of the passband. This paper presents in detail the design considerations and guidelines, as well as analysis of the filter performance in the presence of nonidealities such as parasitics and imperfect clock signal shape. The proposed filter is implemented with high-Q N-path filter blocks in a 65-nm CMOS process. The passband of the filter is tunable from 0.1 to 1.4 GHz with a 3-dB bandwidth of 9.8-10.2 MHz, a gain of 21.5-24 dB, a noise figure of 3-4.2 dB, and a total power consumption of 50-73 mW. TZs are created on both sides of the passband with a minimal offset of 25 MHz and are tunable across a 20-MHz range with up to a 60-dB rejection. The measured blocker 1-dB compression point is 8 dBm and the OOB IIP3 is 23 dBm. The reported filter provides a promising on-chip filtering solution for multistandard multifrequency SDR applications with improved interference mitigation capabilities.

This paper presents a novel dielectric waveguide based G-band interconnect. By using a new transition of microstrip line to dielectric waveguide, the interconnect achieves low insertion loss and wide bandwidth. The measured minimum insertion loss is 4.9 dB with 9.7 GHz 1-dB bandwidth. Besides, the structure is based on standard micromachined processing and easy to integrate with conventional packaging.