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2. Design of Low Inductance Busbar for 500 kVA Three-Level ANPC Converter

Author

Gui, Handong, Zhang, Zheyu, Chen, Ruirui, Niu, Jiahao, Wang, Fred, Tolbert, Leon M, Costinett, Daniel J, Blalock, Benjamin J, and Choi, Benjamin B

Subjects
Aircraft Propulsion And Power
Abstract

The adoption of SiC devices in high power applications enables higher switching speed, which requires lower circuit parasitic inductance to reduce the voltage overshoot. This paper presents the design of a busbar for a 500 kVA three-level active natural clamped converter. The layout of the busbar is discussed in detail based on the analysis of the multiple commutation loops, magnetic cancelling effect, and DC-link capacitor placement. The loop inductance of the designed busbar is verified with simulation, impedance measurements and converter experiment. The results can match with each other and the inductances of small and large loop are 6.5 nH and 17.5 nH respectively, which is significantly lower than the busbars of NPC type converters in other references.

Published
2019

3. A Simple Control to Reduce the Voltage Stress of Non-Conducting Switches in Three-Level ANPC Converter

Author

Gui, Handong, Chen, Ruirui, Niu, Jiahao, Tolbert, Leon M, Wang, Fred, Costinett, Daniel J, Blalock, Benjamin J, and Choi, Benjamin B

Subjects
Electronics And Electrical Engineering
Abstract

With the development of wide band-gap (WBG) technology, the switching speed of power semiconductor devices is increased, which makes circuits more sensitive to parasitics. For three-level active neutral point clamped (3L-ANPC) converters, the over-voltage of non-conducting switches can be an issue. This paper analyzes the multiple commutation loops in 3L-ANPC converter and summarizes the impact factors of the over-voltage for the non-conducting switch. It is found that the nonlinearity of the output capacitance of the device can significantly influence the over-voltage. A simple control without introducing any additional hardware circuit is proposed to attenuate the impact of the nonlinearity. With the proposed control, the peak over-voltage of the non-conducting switch can be reduced significantly. Multi-pulse test is conducted for a 3L- ANPC converter built with silicon carbide (SiC) MOSFETs. The testing results show that the peak over-voltage decreases from 892 V to 624 V with the proposed control. More detailed analysis and experimental results will be provided in the final paper.

Published
2019

4. Modeling of Multi-Loops Related Device Turn-On Overvoltage in 3L-ANPC Converters

Author

Gui, Handong, Chen, Ruirui, Niu, Jiahao, Tolbert, Leon M, Wang, Fred, Costinett, Daniel J, Blalock, Benjamin J, and Choi, Benjamin B

Subjects
Electronics And Electrical Engineering
Abstract

The analytical model for the device drain-source turn-on overvoltage in three-level active neutral point clamped (3L-ANPC) converters is established in this paper. Considering the two commutation loops in the converter, the relationship between the overvoltage and the loop inductances is evaluated. The line switching frequency device usually exhibits higher overvoltage, while the high switching frequency device is not strongly influenced by the multiple loops. A 500 kVA 3L-ANPC converter using SiC MOSFETs is tested, and the model is verified with the experimental results.

Published
2019

12. Development of High-Power High Switching Frequency Cryogenically Cooled Inverter for Aircraft Applications

Author

Gui, Handong, primary, Zhang, Zheyu, additional, Chen, Ruirui, additional, Ren, Ren, additional, Niu, Jiahao, additional, Li, Haiguo, additional, Dong, Zhou, additional, Timms, Craig, additional, Wang, Fei, additional, Tolbert, Leon M., additional, Blalock, Benjamin J., additional, Costinett, Daniel, additional, and Choi, Benjamin B., additional

Published
2020
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18. MW-Class Cryogenically-Cooled Inverter for Electric Aircraft Applications

Author

Wang, Fred, primary, Chen, Ruirui, additional, Gui, Handong, additional, Niu, Jiahao, additional, Tolbert, Leon, additional, Costinett, Daniel, additional, Blalock, Benjamin, additional, Liu, Shengyi, additional, Hull, John, additional, Williams, John, additional, Messer, Timothy, additional, Solodovnik, Eugene, additional, Paschedag, Darren, additional, Khozikov, Vyacheslav, additional, Severns, Christopher, additional, Karimi, Kamiar, additional, and Choi, Benjamin B., additional

Published
2019
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24. A Simple Control to Reduce Device Over-Voltage Caused by Non-Active Switch Loop in Three-Level ANPC Converters

Author

Gui, Handong, primary, Zhang, Zheyu, additional, Chen, Ruirui, additional, Ren, Ren, additional, Niu, Jiahao, additional, Liu, Bo, additional, Li, Haiguo, additional, Dong, Zhou, additional, Wang, Fred, additional, Tolbert, Leon M., additional, Blalock, Benjamin J., additional, Costinett, Daniel J., additional, and Choi, Benjamin B., additional

Published
2019
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28. Multi-Commutation Loop Induced Over-voltage Issue on Non-active Switches in Fast Switching Speed Three-Level Active Neutral Point Clamped Phase Leg

Author

Ren, Ren, primary, Zhang, Zheyu, additional, Liu, Bo, additional, Chen, Ruirui, additional, Gui, Handong, additional, Niu, Jiahao, additional, Wang, Fred, additional, Tolbert, Leon M., additional, Blalock, Benjamin J., additional, Costinett, Daniel J., additional, and Choi, Benjamin B., additional

Published
2018
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42. Characterization and Failure Analysis of 650-V Enhancement-Mode GaN HEMT for Cryogenically Cooled Power Electronics

Author

Ren, Ren, Gui, Handong, Zhang, Zheyu, Chen, Ruirui, Niu, Jiahao, Wang, Fei, Tolbert, Leon M., Costinett, Daniel, Blalock, Benjamin J., and Choi, Benjamin B.

Abstract

In order to evaluate the feasibility of newly developed gallium nitride (GaN) devices in a cryogenically cooled converter, this article characterizes a 650-V enhancement-mode GaN high-electron mobility transistor (GaN HEMT) at cryogenic temperatures. The characterization includes both static and dynamic behaviors. The results show that this GaN HEMT is an excellent device candidate to be applied in cryogenic-cooled applications. For example, transconductance at cryogenic temperature (93 K) is 2.5 times higher than one at room temperature (298 K), and accordingly, peak di/dt during turn-on transients at cryogenic temperature is around 2 times of that at room temperature. Moreover, the ON-resistance of the channel at the cryogenic temperature is only one-fifth of that at room temperature. The corresponding explanations of performance trends at cryogenic temperatures are also given from the view of semiconductor physics. In addition, several device failures were observed during the dynamic characterization of GaN HEMTs at cryogenic temperatures. The ultrafast switching speed-induced high di/dt and dv/dt at cryogenic temperatures amplify the negative effects of parasitics inside the switching loop. Based on failure waveforms, two failure modes were classified, and detailed failure mechanisms caused by ultrafast switching speed are given in this article.

Published
2020
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43. Methodology to Improve Switching Speed of SiC MOSFETs in Hard Switching Applications

Author

Gui, Handong

Subjects
SiC, Switching speed, Multi-level converter, Parasitics, Gate drive
Abstract

To meet the higher efficiency and power density requirement for power converters, the switching speed of power devices is preferred to increase. Thanks to silicon carbide (SiC) power MOSFETs, their intrinsic superior switching characteristics compared with silicon IGBTs makes it possible to run converters at faster switching speed in hard switching applications. Nevertheless, the switching speed is not only dependent on the device’s characteristics, but also strongly related to the circuit like gate drive and parasitics. To fully utilize the potential of SiC MOSFETs, the impact factors limiting the switching speed are required to be understood. Specific solutions and methods need to be developed to mitigate the influence from these impact factors.The characterization of the switching speed for SiC MOSFETs with different current ratings is conducted with double pulse test (DPT) first. Based on the result, the impact factors of switching speed are evaluated in detail.According to the evaluation, the switching speed of SiC discrete devices with low current rating is mainly limited by the gate drive capability. A current source gate drive as well as a charge pump gate drive are proposed, which can provide higher current during the switching transient regardless of the low transconductance and large internal gate resistance of SiC discrete devices.For SiC power modules with high current rating, the switching speed is mainly determined by the device drain-source overvoltage resulting from circuit parasitics. An analytical model for the multiple switching loops related overvoltage in 3L-ANPC converters is established. A simple modulation is developed to mitigate the effect of the non-linear device output capacitance, which helps reduce the overvoltage and enables higher switching speed operation of SiC power modules.Furthermore, the layout design methodology for three-level converters concerning the multiple commutation loops is introduced. The development of a laminated busbar for a 500 kVA 3L-ANPC converter with SiC power modules is presented in detail.Finally, a SiC based 1 MW inverter is built and tested to operate at cryogenic temperature. The proposed control and busbar above are utilized to increase the switching speed of the SiC power module.

Published
2020

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