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Your search keyword '"Guo, Kaile"' showing total 4 results
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4 results on '"Guo, Kaile"'

1. A 32 Gb/s Low Power Little Area Re-timer with PI Based CDR in 65 nm CMOS Technology

Author

Pang, Zhengbin, Lv, Fangxu, Tang, Weiping, Lai, Mingche, Guo, Kaile, Wu, Yuxuan, Liu, Tao, Wu, Miaomiao, Lu, Dechao, Filipe, Joaquim, Editorial Board Member, Ghosh, Ashish, Editorial Board Member, Prates, Raquel Oliveira, Editorial Board Member, Zhou, Lizhu, Editorial Board Member, Dong, Dezun, editor, Gong, Xiaoli, editor, Li, Cunlu, editor, Li, Dongsheng, editor, and Wu, Junjie, editor

Published
2020
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3. A Cryo-CMOS, Low-Power, Low-Noise, Phase-Locked Loop Design for Quantum Computers.

Author

Xin, Kewei, Lai, Mingche, Lv, Fangxu, Guo, Kaile, Pang, Zhengbin, Xu, Chaolong, Zhang, Geng, Wang, Wenchen, and Li, Meng

Subjects
COMPUTER engineering, PHASE-locked loops, QUANTUM computers, VOLTAGE-controlled oscillators, ON-chip charge pumps, QUANTUM computing, ELECTRIC power filters, NOISE, ELECTROSTATIC discharges
Abstract

This paper analyzes the performance requirements that need to be met by a clock generator applied to a low-temperature quantum computer and analyzes the negative effects on the clock generator circuit under low-temperature conditions. In order to meet the performance requirements proposed in this paper and suppress the negative effects brought about by the low temperature, a clock generator for ultra-low-temperature quantum computing is designed. This clock generator is designed by using F-CLASS Voltage Controlled Oscillator (VCO), power filter, tail resistor, differential charge pump, and other techniques. And the noise characteristics of the clock generator are analyzed by Impulse Sensitive Function (ISF) and simulation results. After simulation tests, the average power consumption of the clock generator designed in this paper is 7 mW, the phase noise is −121 dBc/Hz@1 MHz, and the jitter is 62 fs. The performance of the clock generator meets the performance requirements proposed in this paper, and the reduction in the corner frequency proves that the circuit will have better performance at low temperatures. [ABSTRACT FROM AUTHOR]

Published
2023
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4. Frequency Domain Modeling and Performance Analysis of Injection-Locked LC Oscillator

Author

Xin, Kewei, Lai, Mingche, Lv, Fangxu, Zheng, Xuqiang, Guo, Kaile, Pang, Zhengbin, Xu, Chaolong, Zhang, Geng, Wang, Wenchen, and Li, Meng

Abstract

This brief proposes a frequency domain model for injection-locked LC oscillators by introducing the impulse sensitivity function (ISF) and injection factor, analyzes the effect of the injection pulse width and injection position on oscillator performance based on this model, and derives an equation that can guide the design and optimization of oscillators. The model fills the gap in the field of frequency domain models for injection-locked LC oscillators. Based on the above model, a clock generator circuit structure operating at 14 GHz, combining a phase-locked loop with an injection-locked oscillator, is designed and measured based on a 65-nm cmos process. The circuit achieves better phase noise performance by optimizing the two parameters, which verifies the accuracy of the proposed model.

Published
2024
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