Search

This study presents investigations about the physical mechanisms, origin, and methods to control the pattern dependency in selective epitaxial growth of Si1-xGex (x=0.14–0.32) layers. It is shown with a comprehensive experimental study that the local Si coverage of individual chips on patterned wafers is the main parameter for the layer profile in the epitaxial growth. This was explained by the gas depletion of the growth species in the low velocity boundary layer over the wafer. The gas depletion radius around each oxide opening was in the centimeter range which is related to the boundary layer thickness. The results from these experiments were applied to grow Si0.75Ge0.25 layers with B concentration of 4×1020 cm-3 selectively for elevated source and drains in fully depleted ultrathin body silicon on insulator p metal oxide semiconductor field effect transistor (p-MOSFET) devices. The epitaxy control was maintained over a wide range of device sizes by optimized process parameters in combination with a wafer pattern design consisting of dummy features causing a uniform gas depletion over the chips on the wafer. [ABSTRACT FROM AUTHOR]

The interaction of Ni films with epitaxially grown Si-capped and not capped Si0.75Ge0.25 layers on Si(100) at 500 °C leads to the formation of NiSi1-uGeu films as a bilayer NiSi on NiSi0.75Ge0.25 with a rather clear compositional boundary. In the absence of a Si cap at the surface, NiSi0.75Ge0.25 is formed on NiSi. Epitaxy of NiSi on NiSi0.75Ge0.25, and vice versa, occurs across the compositional boundary. The crystallographic orientation of the NiSi1-uGeu films is strongly affected by the initial layer thicknesses and the layer sequence. Without a Si cap, the NiSi1-uGeu films show an increased fiber texture with increasing Si0.75Ge0.25 thickness. In the presence of a Si cap, on the other hand, the texture collapses into a random orientation already for thin caps. Rapid diffusion of Ge at 500 °C results in the presence of some Ge at the NiSi/Si interface for a NiSi0.75Ge0.25/NiSi/Si structure. This diffusion is accompanied by an increased roughness at the NiSi/Si interface, as compared to the quite flat NiSi/Si interface in the absence of Ge. For thin Si caps, severe interface roughening with thick NiSi0.75Ge0.25 grains protruding deeply into the remaining Si0.75Ge0.25 is observed. [ABSTRACT FROM AUTHOR]

The influence of carbon and germanium on phase transformation and sheet resistance of Ni on epitaxially grown Si[sub 1-x-y]Ge[sub x]C[sub y] (0<=x<=0.24 and 0<=y<=0.01) layers annealed in a temperature range of 360 to 900 °C has been investigated. The role of strain relaxation or compensation in the reaction of Ni on Si[sub 1-x-y]Ge[sub x]C[sub y] layers due to Ge or C out-diffusion to the underlying layer during the phase transformation has also been investigated. The formed NiSiGe layers were crystalline, with strong (020)/(013) growth orientation in the direction, but the thermal stability decreased rapidly with increasing Ge amount due to agglomeration. However, this thermal behavior was shifted to higher annealing temperatures when carbon was incorporated in the SiGe layers. A carbon accumulation at the interface of NiSiGeC/SiGeC has been observed even at low-temperature annealing, which is suggested to retard the phase transformation and agglomeration of Ni/SiGeC system. © 2004 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Abstract: The selective growth of Si1− x Ge x structures () on patterned substrates aimed for channel layer application in metal oxide semiconductor field effect transistor (MOSFET) structures by using chemical vapor deposition (CVD) has been investigated. By optimizing the growth parameters, the surface roughness of these structures was improved and layers with better epitaxial quality was obtained. Furthermore, two methods are proposed to decrease the pattern-dependency of the epitaxy process. The key point in these methods is based on the reduction of surface diffusion of the adsorbed species on the oxide. This can be obtained by introducing square polycrystalline Si stripes around the oxide openings acting as diffusion barriers. Subsequently, chemical mechanical polishing was performed to remove the polycrystalline stripe on the oxide. Evaluation of the proposed solutions for issues such as defect generation and the possibility for integration in device structures have also been performed. [Copyright &y& Elsevier]

The epitaxial quality of non-selective and selective deposition of Si1−x−yGexCy (0≤x≤0.30, 0≤y≤0.02) layers has been optimized by using high-resolution reciprocal lattice mapping (HRRLM). The main goal was to incorporate a high amount of substitutional carbon atoms in Si or Si1−xGex matrix without creating defects. The carbon incorporation behavior was explained by chemical and kinetic effects of the reactant gases during epitaxial process. Although high quality epitaxial Si1−yCy layers can be deposited, lower electron mobility compared to Si layers was observed. [Copyright &y& Elsevier]

Abstract: The influence of chip layout (Si coverage and geometry) on the pattern dependency of selective epitaxy of SiGe layers has been investigated. The variation of Ge content and the growth rate have been investigated from a chip-to-chip (local effect) or wafer-to-wafer. The results are described by transport and diffusion of the reactant molecules over the chips during epitaxy. Our investigations are focused on the origin of pattern dependency of the deposition and also propose methods to control this growth behavior. [Copyright &y& Elsevier]