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The demand for high-performance graphics systems used for artificial intelligence, cloud game, and virtual reality continues to grow; this trend requires graphics systems to achieve ever higher bandwidths. This article proposes a GDDR6 dynamic random access memory (DRAM) with a half-rate clocking architecture and optimized receiver and transmitter to improve high-speed operation. Furthermore, this article adopts a staggered PAD using the redistribution layer (RDL) to reduce the distance to four PADs; it enables the mitigation of bandwidth limitation of half-rate clocking, a lower phase mismatch, and a reduced propagation delay. The proposed half-rate clocking-based GDDR6 DRAM achieves 24 Gb/s/pin on a 1.35-V DRAM process. Also, the power-supply-induced-jitter (PSIJ) value is improved from 9.97 to 3.22 ps, compared to a GDDR6 design using a quarter-rate clocking. In addition, the phase mismatch of the proposed clock distribution network (CDN) is reduced compared to the conventional CDN, resulting in an improvement of the 3-σ value of the phase skew from 4.16 to 2.25 ps.

A 1.3–4-GHz quadrature-phase digital delay-locked loop (DDLL) with sequential delay control and a reconfigurable delay line is designed using a 28 nm CMOS process. The time resolution of the DDLL is reduced by updating the delay code sequentially. A bidirectional shift register enables this operation with low power, resulting in bang-bang jitter that is three times smaller than that of a conventional DDLL. Conventional delay control is replaced with sequential delay control after a DDLL lock to reduce the locking time. A DDLL with a wide operation range is achieved with a reconfigurable delay line. Unlike the conventional DDLL, the minimum delay difference is adjustable in the proposed structure. To achieve a wide frequency range, the minimum delay difference of the quadrature clock is increased or decreased in three operation modes. To compensate for local variations in the CMOS process, a skew calibration circuit is implemented with the DDLL. The hardware cost of skew calibration is minimized with the proposed DDLL because it shares the subblocks for sequential delay control. The average phase difference from the quadrature clocks becomes the reference for the 90° phase for skew correction. A duty-cycle corrector (DCC) is implemented by collecting the positive edges of the quadrature-phase clocks. The DDLL consumes 6.5 mW at the maximum clock frequency of 4 GHz. The peak-to-peak jitter is improved from 15.6 to 12.5 ps with sequential delay control.

This brief presents a power- and area-efficient forwarded-clock (FC) receiver with a delay-locked loop (DLL)-based self-tracking loop for unmatched memory interfaces. In the proposed FC receiver, the self-tracking loop is composed of two-stage cascaded DLLs to support a burst mode. The proposed scheme compensates for a delay drift neither by relying on data (DQ) transitions nor by re-training but with a write training of the memory controller to fine-tune a data strobe (DQS) path delay through DLLs. The proposed FC receiver is fabricated in the 65-nm CMOS technology and the active area including 4 DQ lanes is 0.0329 mm2. After the write training is completed at supply voltage of 1 V, the measured timing margin remains larger than 0.31 UI when the supply voltage drifts in the range of 0.94 V and 1.06 V from the training voltage, 1 V. At the data rate of 6.4 Gb/s, the proposed FC receiver achieves an energy efficiency of 0.45 pJ/bit.

This paper presents a data (DQ) receiver for HBM3 with a self-tracking loop that tracks a phase skew between DQ and data strobe (DQS) due to a voltage or thermal drift. The self-tracking loop achieves low power and small area by utilizing an analog-assisted baud-rate phase detector. The proposed pulse-to-charge (PC) phase detector (PD) converts the phase skew to a voltage difference and detects the phase skew from the voltage difference. An offset calibration scheme that can compensates for a mismatch of the PD is also proposed. The proposed calibration scheme operates without any additional sensing circuits by taking advantage of the write training of HBM. Fabricated in 65 nm CMOS, the DQ receiver shows a power efficiency of 370 fJ/b at 4.8 Gb/s and occupies 0.0056 mm2. The experimental results show that the DQ receiver operates without any performance degradation under ${a}\pm 10$% supply variation.

A four-bit four-wire four-level (4B4W4L) single-ended parallel transceiver for the point-to-point DRAM interface achieved a peak reduction of $\sim 10$ dB in the electromagnetic interference (EMI) H-field power, compared to a conventional 4-bit parallel binary transceiver with the same output driver power of transmitter (TX) and the same input voltage margin of receiver (RX). A four-level balanced coding is used in this work to minimize the simultaneous switching noise at TX, to utilize a differential sensing without a reference voltage at RX, to maintain the pin efficiency of 100%, and also to reduce EMI by setting the sum of currents through the four wires to be zero. A capacitive pre-emphasis scheme modified for four-level signaling is also used at TX to compensate for inter-symbol interference. The transmitted four-level signals are recovered by six differential comparators with an offset compensation and a decoder at RX. The proposed transceiver chip fabricated in a 65 nm CMOS process consumes 2.39 pJ/bit with a 1.2 V supply and a 2 inch FR4 channel at 8 Gb/s.

A feedback edge combiner is proposed for the duty-cycle corrector (DCC) of a delay locked loop (DLL) to increase the range of allowed input duty cycle. The feedback edge combiner generates the rising edge of a DCC output at the rising edge of an input clock. It generates the falling edge of the DCC output at the rising edge of a feedback clock that is a half-period-delayed signal of the DCC output. A dual-delay-line digitally controlled delay line (DCDL) is used for seamless boundary switching. The chip area of the DCDL is reduced by around 46% by employing the architecture of two short coarse delay lines followed by a fine phase mixer (FPM) and a long coarse delay line in series instead of the architecture of two long coarse delay lines followed by an FPM. The measurements on the chip fabricated in the 65-nm CMOS show the allowed input duty cycle in the range from 20% to 80%; root-mean-square and peak-to-peak jitters of 2.69 and 14.0 ps, respectively, at 2 GHz and 1.2 V; and the operating frequency range from 0.12 to 2.0 GHz at 1.2 V. The measured power consumption is 3.3 mW/GHz at 1.2 V. The chip area is 0.059 mm 2.

The demands on higher bandwidth with reduced power consumption in mobile market are driving mobile DRAM with advanced design techniques. Proposed LPDDR4 in this paper achieves over 39% improvement in power efficiency and over 4.3 Gbps data rate with 1.1 V supply voltage. These are challenging targets compared with those of LPDDR3. This work describes design schemes employed in LPDDR4 to satisfy these requirements, such as multi-channel-per-die architecture, multiple training modes, low-swing interface, DQS and clock frequency dividing, and internal reference for data and command-address signals. This chip was fabricated in a 3-metal 2y-nm DRAM CMOS process.

This paper presents a novel floating tap termination (FTT) scheme with inverted data bus inversion (iDBI_AC) and floating tap forcing (FTF) to remove the DC current path, leading to reduction of static current. The iDBI_AC and FTF are proposed to resolve common-mode stabilization issues for the floating tap termination scheme during transmitting unbalanced data patterns. Power efficiency with the proposed scheme using 0.6V I/O supply and a 0.13-um technology is measured as 0.127mW/Gbps/pin, which is 61% lower than that of a low tap termination (LTT) scheme used in LPDDR4X. In addition to the power benefit, measurement results present that the proposed scheme leads to achieve 7Gbps data-rate without penalty of signal integrity issues and the iDBI_AC minimizes inter-symbol interference (ISI).

A low-energy single-ended duobinary transceiver is proposed for the point-to-point DRAM interface with an energy efficiency of 0.56 pJ/bit at 7 Gb/s. The transmitter power is reduced by decreasing the signal swing of transmission channel to 80 mV and replacing the multiplexer and the binary output driver in the transmitter by a duobinary output driver. A trans-impedance amplifier (TIA) is used at the receiver end of transmission channel. The TIA works as a receiver termination and also amplifies the input signal for subsequent processing. Analysis of the feedback loop delay and the nonlinearity of the TIA shows that they do not impose serious problems. The TIA output signal is applied to a duobinary-to-NRZ converter, which is implemented by using a direct feedback 1-tap DFE circuit with a tap-coefficient of 1.0. The reference voltage of the duobinary-to-NRZ converter is calibrated automatically to enable a small-swing signaling. The proposed transceiver chip in a 65 nm CMOS process works at 4.5 Gb/s with a 3" FR4 microstrip line, and at 7 Gb/s with a 0.6" FR4.

By using the clock timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). Compared to the authors’ prior work, the delay block circuit is simplified by combining a delay block with a minimal number of stages and a 3-to-1 multiplexer. The d elayblock generates three clock signals with different delays corresponding to the channel delay of three different signal modes. The 3-to-1 multiplexer selects one of the three clock signals for TX timing depending on the signal mode. The TX is implemented by using a 0.18 ㎛ CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps. Compared to the authors’ prior work, the amount of RX Jitter reduction increases from 28 ps to 38 ps by using the improved implementation.

Serpentine microstrip lines are proposed to eliminate the far-end crosstalk in parallel high-speed interfaces by increasing the capacitive coupling ratio to equal the inductive coupling ratio. Zero far-end crosstalk voltage waveform and zero crosstalk-induced jitter (CIJ) were achieved on an FR4 printed circuit board, by adjusting the unit section length of the serpentine structure. Application of the proposed serpentine microstrip lines to the 2-drop stub series terminated logic DRAM channel increased the maximum data rate from 0.9 to 1.4 Gb/s and reduced CIJ by ~ 78 ps at 3.3 Gb/s.

By using the data timing control at transmitter (TX) side, the crosstalk-induced jitter (CIJ) is compensated in a 4 Gbps single-ended transmitter with 3-bit parallel data. CIJ is induced by the propagation velocity difference between the signal modes of parallel transmission lines. This velocity difference was compensated for by sending data early or late at TX according to the signal modes, so that the signals of different modes arrive at receiver at the same time. The proposed TX was implemented by using a 0.18 mum CMOS process. The parallel transmission lines used in the measurements are 4-inch long, have the minimum-allowed spacing between transmission lines to maximize CIJ. CIJ was measured to be reduced by about 50% from 53 ps to 27 ps at 4 Gbps excluding the random jitter component of 72 ps added at the TX side. The scheme used in this work can be expanded to more than three transmission lines.

A serpentine guard trace is proposed to reduce the peak far-end crosstalk voltage and the crosstalk induced timing jitter of parallel microstrip lines on printed circuit boards. The vertical sections of the serpentine guard increase the mutual capacitance without much changing the mutual inductance between the aggressor and victim lines. This reduces the difference between the capacitive and inductive couplings and hence the far-end crosstalk. Comparison with the no guard, the conventional guard, and the via-stitch guard shows that the serpentine guard gives the smallest values in both the peak far-end crosstalk voltage and the timing jitter. The time domain reflectometer (TDR) measurement shows that the peak far-end crosstalk voltage of serpentine guard is reduced to 44% of that of no guard. The eye diagram measurement of pseudo random binary sequence (PRBS) data shows that the timing jitter is also reduced to 40% of that of no guard.

A 4.35Gb/s/pin LPDDR4 I/O interface with multi-VOH level, equalization scheme and Duty-Training Circuit (DTC) is presented. A Low Voltage-Swing Terminated Logic (LVSTL) driver using 4-to-1 multiplexer is implemented to the transmitter. A DTC to adjust the CK duty is implemented to the receiver. In addition, a ZQ calibration scheme for Multi-VOH level is also presented. Designed schemes are compatible with the LPDDR4 standard. Power efficiency for the I/O interface is about 2.3mW/Gb/s/pin with 1.1V supply in 2y-nm DRAM process, which is 31% lower than that of LPDDR3.

The transient far-end crosstalk voltage and the crosstalk-induced jitter of dual in-line memory module (DIMM) connectors are reduced by about 80% by increasing the mutual capacitance between DIMM connector pins with the additional interdigitated-comb-shaped metal-stub patterns on the motherboard. It was confirmed by the far-end crosstalk voltage waveform measurements using TDR and the eye diagram measurements at the data rates of 15 Mbps, 100 Mbps, and 3 Gbps. This reduction technique can be applied to the connectors where the inductive coupling ratio is larger than the capacitive coupling ratio.

By using the data timing control at transmitter (TX), the crosstalk-induced jitter (CIJ) is compensated for in the 2-bit parallel data transmission through the coupled microstrip lines on printed circuit board (PCB). The difference in propagation velocity with the signal modes (odd, static, even) is compensated for by sending data earlier or later at TX according to the signal modes, so that the signals of different modes arrive at receiver (RX) at the same time. This transmitter is implemented by using the delay block with low jitter and a 3:1Mux to select one CLKT of the generated three different sampling CLKD, in advance. The TX is implemented by using a 0.18 μm CMOS process. The measurement shows that the TX reduces the RX jitters by about 38 ps at the data rates from 2.6 Gbps to 3.8 Gbps.

A single-ended transmitter eliminates the crosstalk-induced jitter at receiver by controlling the slew rates of the signal at transmitter for the even and odd modes of two parallel coupled microstrip lines. The transmitter chip in a 0.18 µm CMOS process reduces the total RX jitter by about 38 ps (53%) for the data rates from 2.6 to 5 Gbps, and increases the horizontal eye-opening (BER < 1E-12) by about 21% at 5 Gbps.

A serpentine guard trace located between two microstrip transmission lines reduced the peak far-end crosstalk voltage and the difference in propagation delay times between the even and odd mode signals by more than half of those of the no guard case, respectively, without the PCB area overhead. This reduction was achieved by increasing mutual capacitance without changing mutual inductance.