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This paper is concerned with the problem of collision-free path planning for manipulators in multi-obstacle scenarios. Aiming at overcoming the deficiencies of existing algorithms in excessive time consumption and poor expansion quality, a path planning algorithm named Fast Bi-directional Rapidly-exploring Random Tree (FBi-RRT) with novel heuristic node expansion is proposed, which includes a selective-expansion strategy and a vertical-exploration strategy. The selective-expansion strategy is designed to guide the selection of the nearest-neighbor node to avoid the repeated expansion failure, thereby shortening the overall planning time. Also, the vertical-exploration strategy is developed to regulate the expansion direction of the collision nodes to escape from the obstacle space with less blindness, thus improving the expansion quality and further reducing time cost. Compared with previous planning algorithms, FBi-RRT can generate a feasible path for manipulators in a drastically shorter time. To validate the effectiveness of the proposed heuristic node expansion, FBi-RRT is conducted on a 6-DOF manipulator and tested in five scenarios. The experimental results demonstrate that FBi-RRT outperforms the existing methods in time consumption and expansion quality. [ABSTRACT FROM AUTHOR]

Emulating synaptic behavior using the three-terminal and ion-coupled transistors is considered as a promising strategy for the realization of neuromorphic devices. Meanwhile, one-dimensional (1-D) nanostructures show great potential for the fabrication of flexible electronic devices. In this work, 1-D indium oxide (In2O3) nanofibers were fabricated by the electrospinning (ES), and the flexible and compatible synaptic transistor based on In2O3 nanofibers was integrated on polyimide (PI) substrate. The synaptic behaviors, such as the short-term plasticity (STP) and long-term plasticity (LTP), are simulated by the synaptic transistor with chitosan solution as the gate dielectric. The fabricated synaptic transistor exhibits good biocompatibility and environmental compatibility, and the pattern recognition rate of the simulated device array by the Mixed National Institute of Standards and Technology (MNIST) database of the handwritten digits is confirmed to be as high as 92%. [ABSTRACT FROM AUTHOR]

Thin-film transistors (TFTs) with bilayer channels were used to improve the field-effect mobility and bias stress stability of the TFTs. Homogeneous structures were fabricated by the combination of a carrier deficient layer made of In2O3 thin film annealed in oxygen atmosphere (InO:O) and an electron injection layer made of In2O3 thin film annealed in air (InO:A). Compared with the InO:A/InO:A TFT with only air annealing, the field-effect mobility of InO:O/ InO:A TFT with two-step annealing process was improved from 0.04 to 5.11 cm2/Vs, the on/off current ratio was ameliorated from 4.6 × 105 to 7.6 × 107 A, while the VTH is decreased from 12.5 to 4.7 V under the positive bias stressing (PBS). It is confirmed that the excessive oxygen vacancies are produced by annealing the thin film in the air. The electrical performance of the InO:O/InO:A TFTs with two-step annealing process is greatly improved due to the formation of a low defect state and high carrier concentration electron transport layer, through the combination of the carrier transport layer and the carrier injection layer. These optimized electrical properties indicate an important step toward achieving transparent, high performance, and low-temperature metal oxides TFTs. [ABSTRACT FROM AUTHOR]