Search

Titanium Silicide (TiSi2 is a primary contact material with low-resistance contact characteristics used in nanodevices. However, the rapid scaling trend requires further improvement to achieve both high thermal stability and low contact resistivity. Herein, a method for simultaneously improving the contact resistivity and thermal stability of the TiSi2 /Si interface is proposed by inserting a Ta interlayer into Ti/p-Si. The Ta-interlayered TiSi2 (Ta IL TiSi2) achieves an improved contact resistivity by approximately 7.9 times compared to that without the Ta interlayer. This remarkable improvement is due to the smooth contact morphology resulting from the suppressed excess diffusion of Ti and Si and dopant segregation at the TiSi2/Si interface. Particularly, because additional reaction during post annealing is minimized by the Ta interlayer, Ta IL TiSi2 shows a low sheet resistance of $3.71~\Omega /\Box $ even after post annealing at 600 °C & 30 min, which is much lower than the conventional TiSi2 scheme under the same annealing conditions. These results are expected to provide insights into state-of-the-art CMOS-based devices that require both low contact resistivity and better thermal margins.

Although molybdenum disulfide (MoS2) is highlighted as a promising channel material, MoS2-based field-effect transistors (FETs) have a large threshold voltage hysteresis (ΔVTH) from interface traps at their gate interfaces. In this work, the ΔVTHof MoS2FETs is significantly reduced by inserting a 3-aminopropyltriethoxysilane (APTES) passivation layer at the MoS2/SiO2gate interface owing to passivation of the interface traps. The ΔVTHis reduced from 23 to 10.8 V by inserting the 1%-APTES passivation layers because APTES passivation prevents trapping and detrapping of electrons, which are the major source of the ΔVTH. The reduction in the density of interface traps (Dit) is confirmed by the improvement of the subthreshold swing (SS) after inserting the APTES layer. Furthermore, the improvement in the synaptic characteristics of the MoS2FET through the APTES passivation is investigated. Both inhibitory and excitatory postsynaptic currents (PSC) are increased by 33% owing to the reduction in the ΔVTHand the n-type doping effect of the APTES layer; moreover, the linearity of PSC characteristics is significantly improved because the reduction in ΔVTHenables the synaptic operation to be over the threshold region, which is linear. The application of the APTES gate passivation technique to MoS2FETs is promising for reliable and accurate synaptic applications in neuromorphic computing technology as well as for the next-generation complementary logic applications.

Schottky barrier height (SBH) engineering of contact structures is a primary challenge to achieve high performance in nanoelectronic and optoelectronic applications. Although SBH can be lowered through various Fermi-level (FL) unpinning techniques, such as a metal/interlayer/semiconductor (MIS) structure, the room for contact metal adoption is too narrow because the work function of contact metals should be near the conduction band edge (CBE) of the semiconductor to achieve low SBH. Here, we propose a novel structure, the metal/transition metal dichalcogenide/semiconductor structure, as a contact structure that can effectively lower the SBH with wide room for contact metal adoption. A perpendicularly integrated molybdenum disulfide (MoS2) interlayer effectively alleviates FL pinning by reducing metal-induced gap states at the MoS2/semiconductor interface. Additionally, it can induce strong FL pinning of contact metals near its CBE at the metal/MoS2interface. The technique using FL pinning and unpinning at metal/MoS2/semiconductor interfaces is first introduced in the MIS scheme to allow the use of various contact metals. Consequently, significant reductions of the SBH from 0.48 to 0.12 eV for GaAs and from 0.56 to 0.10 eV for Ge are achieved with several different contact metals. This work significantly reduces the dependence on contact metals with lowest SBH and proposes a new way of overcoming current severe contact issues for future nanoelectronic and optoelectronic applications.

The difficulty in Schottky barrier height (SBH) control arising from Fermi-level pinning (FLP) at electrical contacts is a bottleneck in designing high-performance nanoscale electronics and optoelectronics based on molybdenum disulfide (MoS2). For electrical contacts of multilayered MoS2, the Fermi level on the metal side is strongly pinned near the conduction-band edge of MoS2, which makes most MoS2-channel field-effect transistors (MoS2FETs) exhibit n-type transfer characteristics regardless of their source/drain (S/D) contact metals. In this work, SBH engineering is conducted to control the SBH of electrical top contacts of multilayered MoS2by introducing a metal–interlayer–semiconductor (MIS) structure which induces the Fermi-level unpinning by a reduction of metal-induced gap states (MIGS). An ultrathin titanium dioxide (TiO2) interlayer is inserted between the metal contact and the multilayered MoS2to alleviate FLP and tune the SBH at the S/D contacts of multilayered MoS2FETs. A significant alleviation of FLP is demonstrated as MIS structures with 1 nm thick TiO2interlayers are introduced into the S/D contacts. Consequently, the pinning factor (S) increases from 0.02 for metal–semiconductor (MS) contacts to 0.24 for MIS contacts, and the controllable SBH range is widened from 37 meV (50–87 meV) to 344 meV (107–451 meV). Furthermore, the Fermi-level unpinning effect is reinforced as the interlayer becomes thicker. This work widens the scope for modifying electrical characteristics of contacts by providing a platform to control the SBH through a simple process as well as understanding of the FLP at the electrical top contacts of multilayered MoS2.