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Statistical analysis is performed on the totalionizing-dose (TID) response of fourth-generation silicon–germanium heterojunction bipolar transistors, revealing an increasing variance in base current with increasing dose. A 10-fold increase is observed after 2 Mrad(SiO2) of radiation exposure. The postirradiation performance is shown to be poorly correlated with initial performance, revealing potential difficulties for radiation hardness assurance testing. Simple analytical theory is used to demonstrate how TID exacerbates performance variations due to preexisting process-induced variations. Then, technology computer-aided design (TCAD) simulations are used to investigate the fundamental mechanisms driving these statistical changes, particularly process variations associated with the doping profiles. Simulation results reveal potential methods to both predict TID response and mitigate it at the process level. Finally, implications for hardness assurance testing and radiation-tolerant device and circuit design are discussed, especially the need to consider postirradiation variability in the design process for radiation-intense applications.

We present a co-designed Dicke switch and low-noise amplifier (LNA) in which the switch incorporates a transformer-based topology and serves as the input matching network of the LNA. This topology is configured to minimize the amplifier gain mismatch between the two switching states caused by process variations while providing a low noise figure (NF). The circuit is implemented in a 0.13- $\mu \text{m}$ SiGe BiCMOS technology, and it achieves more than 20-dB gain and minimum NF values of 4.5 and 0.58 dB at 300 and 20 K, respectively. It consumes a dc power of 15 mW. The front-end switch presents a peak isolation of 17 dB, and the input return loss is better than 15 dB across 45–70 GHz. A noise source is also coupled to the front-end circuitry to enable on-chip calibration. The noise performance and reliability of several on-chip p-n junctions were characterized, and the one with the highest excess noise ratio was coupled to the front-end circuitry. To the best of our knowledge, the lowest NF of an integrated switch and LNA at ${V}$ -band frequencies is achieved in the present work, along with the first reliability study of on-chip noise sources in a SiGe BiCMOS technology.

Current mirrors (CMs) are essential building blocks for biasing electronic circuits. The present work demonstrates that errors in mirroring ratios increase at cryogenic temperatures, for all types of SiGe HBT and CMOS CMs. The sources of errors are attributed to the mismatch in operating conditions and a combination of process variations and layout effects. In particular, the effects of layout on device current are found to increase significantly at low temperatures, which can potentially contribute more to the CM error than process variations. Among all investigated CM configurations, the simple CM based on large geometry SiGe HBTs is the most versatile option with small errors, a large operational range, and a simple layout.

This investigation examines the physical mechanisms that can increase the variability of both p-n junctions and silicon–germanium heterojunction bipolar transistors (SiGe HBTs) at cryogenic temperatures. The important operative mechanisms responsible for device parameter variability include bandgap narrowing due to heavy doping, mechanical stress, and the Ge profile. The impact of direct tunneling on cryogenic parameter variability in SiGe HBTs is also examined. Measurement results are compared with TCAD simulations to provide additional insights, and possible mitigation methods are discussed.

The cryogenic performance of radiation-hardened radio-frequency (RF) low-noise amplifiers (LNAs) is presented. The LNA, which was originally proposed for the mitigation of single-event transients (SETs) in a radiation environment, uses inverse-mode silicon-germanium (SiGe) heterojunction bipolar transistors (HBTs) in its core cascode stages. In this prototype, the upper common-base SiGe HBT is configured in inverse mode for balanced RF performance and reduced SET sensitivity. In order to better exploit the inverse-mode LNAs in a variety of extreme-environment applications, the RF performance of the LNA was characterized using liquid nitrogen to evaluate cryogenic operation down to 78 K. While the SiGe LNA exhibits acceptable RF performance for all temperature conditions, there is a noticeable gain drop observed at 78 K compared to the conventional forward-mode design. This is attributed to the limited high-frequency performance of an inverse-mode SiGe HBT. As a guideline, compensation techniques, including layout modifications and profile optimization, are discussed for the mitigation of the observed gain degradation.

A HICUM/L0 compact model is extracted for advanced SiGe HBTs operating at 12 K, targeting potential use for control and readout applications in quantum computing. Due to the presence of transistor non-idealities, extraction procedures are modified from room temperature approaches. The resultant compact model shows good accuracy in both small-signal and large-signal prediction when compared to 12 K measurements for a wideband cryogenic low noise amplifier. Important factors for model accuracy are investigated through sensitivity analysis. This is the first demonstration of a DC, small-signal, and large-signal compact model for SiGe HBTs operating at deep cryogenic temperatures.

This paper provides insight into the transport mechanisms of the collector current in SiGe HBTs operating at cryogenic temperatures and compares three technology generations of devices. Based on the experimental data, a method to differentiate direct tunneling from quasi-ballistic transport is proposed. Measurements indicate that direct tunneling becomes more significant at cryogenic temperatures. The effects of technology scaling on the direct tunneling were investigated using TCAD. Direct tunneling was found to be sensitive to the base width and the Ge profile. It is predicted that without an increase in the Ge content, direct tunneling may dominate over quasi-ballistic transport at the limits of technology scaling.

We investigate high current stress mechanisms and demonstrate how Auger hot carriers can damage both oxide interfaces and polysilicon regions of the emitter and base. A new current gain enhancement (CGE) effect is proposed, which involves hot-carrier damage to the polysilicon emitter and extrinsic base leading to the degradation of the associated minority carrier mobilities. We demonstrate the different CGE mechanisms in SiGe HBTs under forward and inverse modes of operation. The hot-carrier damage responsible for CGE at high injection is explored in depth with the help of TCAD simulations. Evidence for this effect has been gathered with good statistical significance from various stress conditions, various technologies, complimentary (NPN + PNP) devices, and from dc and ac measurements. The new polysilicon degradation mechanism proposed in this paper has been generalized and is important for accurately modeling the changes in base resistance and current gain ( $\beta$ ) at high injection, where circuits are typically biased to extract maximum device performance.

Safe-operating-area (SOA) in a high-voltage complementary silicon–germanium (SiGe) (= n-p-n + p-n-p) on silicon-on-insulator (SOI) technology is investigated from 24 °C to 300 °C. Three key reliability degradation regions are identified, including: 1) high-current; 2) mixed-mode; and 3) high-power. The degradation mechanisms, which are operative, including Auger damage, mixed-mode damage, and electrothermal runaway as well as their temperature dependences are identified. Mixed-mode damage exhibits a strong negative temperature coefficient for both n-p-n and p-n-p SiGe heterojunction bipolar transistors (HBTs) up to 300 °C, which leads to an increase in the SOA from a high-voltage perspective. Electrothermal boundaries are also explored by finding ${J}_{C,{\textsf {crit}}}$ and ${V}_{{\textsf {CB}},{\textsf {crit}}}$ across the ${J}_{C}$ – ${V}_{\textsf {CB}}$ plane up to 300 °C. Both n-p-n and p-n-p SiGe HBTs show an increase in the SOA for the electrothermal boundary as temperature increases. High-current-induced damage, on the other hand, exhibits a positive temperature coefficient, which implies that high current drive should carefully be considered when using SiGe HBT circuits operated in a high-temperature environment. However, at very high temperatures (>200°C), the high current damage processes show annealing properties, which implies that at sufficiently high temperatures, annealing can dominate over Auger damage and potentially extend the SOA of the technology.

To support many power management applications in wireless sensor networks, a previously developed model is modified to predict the terminal behaviour of a supercapacitor under a dynamic charging/discharging power profile. In addition, a robust model parameter identification method based on the genetic algorithm is developed to determine the model parameters using a dynamic test and a self-discharge experiment. On the basis of the supercapacitor power input model, charge redistribution related figures of merit are derived and used to evaluate the significance of charge redistribution for supercapacitors with various rated capacitance. The results show that supercapacitors with different sizes share similar charge redistribution phenomenon. Furthermore, the charge redistribution significance is studied from several perspectives to provide guidelines for designing power management techniques that can achieve full potential of the energy stored in the supercapacitors.

We present the first measurement results of a highly scaled, 90-nm silicon–germanium heterojunction bipolar transistor (SiGe HBT) operating at cryogenic temperatures as low as 70 mK. The SiGe HBT exhibits a transistor-like behavior down to 70 mK, but below 40 K, the transconductance suggests the presence of non-equilibrium transport mechanisms. Despite the non-ideal base current at cryogenic temperatures, a $dc$ current gain $(\beta) > 1$ is achieved for $I_{C} > 1$ nA, suggesting that ultra-low-power low-noise amplifiers should be viable. Exposure of the SiGe HBT to strong magnetic fields (±14 T) is also presented to help understand the nature of the non-ideal current.

The single-event transient (SET) response of a W-band (75–110 GHz) radar receiver front-end is investigated in this paper. A new technique to facilitate the SET testing of the high frequency transceivers is proposed and demonstrated experimentally. The entire radar receiver front-end, including the high frequency signal sources and modulators, were designed and fully integrated in 90 nm 300 GHz SiGe process technology (Global Foundries SiGe 9HP). Two-photon absorption (TPA) laser pulses were utilized to induce transient currents in different devices in various circuit blocks. The study shows how short transient pulses from the high frequency tuned circuits are propagated throughout the receiver and are broadened while passing through low-pass filters present at supply nodes and the low-pass filter following the down-conversion mixer, thus affecting the digital data at the output of the receiver. The proposed methodology allows the study of the effect of SETs on the recovered digital data at the output of the high frequency receivers, thus allowing bit error rate calculations. Comprehensive device and circuit level simulations were also performed, and a close agreement between the measurement results and simulation data was demonstrated. To the authors’ best knowledge, this is the first study of SET on full receiver at millimeter-wave (mmW) frequencies.

This paper examines the fundamental reliability differences between n-p-n and p-n-p SiGe HBTs. The device profile, hot carrier transport, and oxide interface differences between the two device types are explored in detail as they relate to device reliability. After careful analysis under identical electrical stress conditions for n-p-n and p-n-p, the differences in activation energies for the damage of the oxide interfaces of the two devices is determined to be the primary cause for accelerated degradation seen in p-n-p SiGe HBTs. An analytical model has been adapted for simulating these aging differences between p-n-p and n-p-n devices. This paper has significant implications for predicting the degradation of complementary SiGe HBTs and even engineering future generations with well-matched n-p-n and p-n-p device-level reliability.

We present measurement results of commercially-available 90-nm SiGe HBTs at 300 K, 78 K, and 7 K. The data reveal increased variability of SiGe HBTs at 78 K and 7 K compared to that at 300 K. The variation of collector current, base current, and DC current gain (β) increase from 5% at 300 K to 50% at 7 K around the average measured values. Transconductance (g m ) variation increases from 0.6% at 300 K to 5% at 7 K. Peak f T variation increases from 2.6% to 7.1%, while the f T at low injection increases from 1.8% at 300 K to 24.9% at 7 K. Increased variability is observed at lower injection levels at 78 K and 7 K and DC parameters tend to have more variation than RF parameters. The implications of increased variability for circuit designs supporting emerging cryogenic applications such as quantum computing are discussed.

This work presents the design of a broadband logarithmic (log) power detector implemented using 130 nm SiGe BiCMOS technology. The proposed log detector uses a pair of common-emitter SiGe HBTs for sensing, and a log amplifier stage is employed to achieve linear-in-dB transfer characteristic. The log detector shows 23 dB dynamic range with -28 dBm minimum input power from 2 GHz to 40 GHz with ±1.5 dB log error. The design consumes 3.2 mW of static DC power with a 2-V supply and consumes less than 7.8 mW of DC power over the input power range. A two-branch log detector design consisting of two identical parallel log detectors with modified output stage is also presented. The two-branch log detector demonstrates 47 dB dynamic range with minimum input power of -53 dBm at 10 GHz with ±1.5 dB log error, with an externally introduced 25 dB power level offset between the inputs of the two branches.

Cryogenic operation of classical memory devices is becoming increasingly important in the context of quantum information processing1,2. In existing lab scale solid state quantum computers (QCs), quantum bits (qubits) are placed inside a dilution-refrigerator at a few mK connected to the control processor at room temperature (300 K) through control cables. However, such approach is not scalable to large number of qubits due to (1) the large thermal leakage because of the large thermal gradient across the control wires, and (2) bandwidth restrictions imposed limited number and long lengths of the wires. On the other hand, QCs require significant classical memory capacity (10–100 GB) and bandwidth to (1) store the arbitrary rotations in quantum algorithms and (2) handle error syndromes that are continuously generated and measured to compensate for the extreme noise sensitivity of the qubits. As such, the existing superconducting memory technologies (such as the Josephson-junction (JJ) based memories and hybrid JJ-CMOS memories) operating at mK cannot be used as the sole memory technology due to their limited memory density and energy efficiency. Cryogenic control architectures of QCs are being actively investigated where the processing and control systems and the memory are organized at different temperatures in a cryogenic refrigerator and the latency of room temperature classical memory is amortized by designing multi-temperature memory hierarchies constrained by the refrigerator cooling power at different temperatures and the bandwidth available from the control wires (Fig 1)1,2. Towards that end, we study the cryogenic properties of zirconia stabilized in the tetragonal phase-the work-horse material of commodity DRAM. Antiferroelectricity was recently discovered in tetragonal zirconia and its alloyed variants3,4 for which this material system can serve as a high endurance, non-volatile memory element through work function engineering.5

A ferroelectric field-effect transistor (FeFET) with scaled dimensions (170 nm and 24 nm of gate width and length, respectively) and a 10 nm thick Si doped HfO 2 ferroelectric in the gate oxide stack are characterized at cryogenic temperatures down to 6.9 K. We observe that a decrease in temperature leads to an increase in the memory window at the expense of an increased program/erase voltage. This is consistent with the increase in the ferroelectric coercive field due to the suppression of thermally activated domain wall creep motion at cryogenic temperatures. However, the observed insensitivity of the location of the memory window with respect to temperature cannot be explained by the current understanding of the device physics of FeFETs. Such temperature dependent studies of scaled FeFETs can lead to useful insights into their underlying device physics, while providing an assessment of the potential of this emerging technology for cryogenic memory applications.

This paper presents and validates a physics-based compact aging model for predictive simulation of hot-carrier degradation in SiGe HBTs. Separate aging functions model the effects of high-field mixed-mode and high-current Auger-hot-carrier stresses and are integrated together to provide predictive capability across a wide bias range. The variation of aging rate with device geometry and the incorporation of multiple parameter shifts due to hot carrier polysilicon degradation are explored. Additionally, aging simulation results of a driver circuit are presented to begin to demonstrate how such models may be incorporated as part of the circuit design process.

In quantum computing, metrology, single-photon counting, and nanomechanics, weak electronic signals at extremely low temperatures need amplification. To this end, the authors build and study silicon-germanium heterojunction bipolar transistors, which offer excellent amplifier characteristics, integrability with silicon quantum electronics, low cost, and manufacturability. Their research at the junction of physics and electrical engineering is a step toward next-generation integrated circuits at the 90-nm scale for this temperature regime.

High-current pulsed stress measurements are performed on SiGe HBTs to characterize the damage behavior and create a comprehensive physics-based TCAD damage model for Auger-induced hot-carrier damage. The Auger hot-carrier generation is decoupled from classical mixed-mode damage and annealing on the output plane by using pulsed stress conditions to modulate the self-heating within the device under stress. The physics of high-current degradation is analyzed, and a temperature dependent degradation model is presented. This model is the first of its kind in both the CMOS and bipolar communities and solves a significant portion of the puzzle for predictive modeling of SiGe HBT safe-operating-area (SOA) and reliability.