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A twisted grain boundary is introduced in the tellurium crystal to effectively block phonon propagation while maintaining high electron mobility for superior thermoelectric properties.

Cation disordering is commonly found in multinary cubic compounds, but its effect on electronic properties has been neglected because of difficulties in determining the ordered structure and defect energetics. An absence of rational understanding of the point defects present has led to poor reproducibility and uncontrolled conduction type. AgBiSe

Directed self-assembly of vertically aligned block copolymer (BCP) thin films has been extensively explored as one of the possible bottom-up routes for sub-10 nm patterning technology. To achieve a vertical orientation, it has been imperative to incorporate neutralization layers to balance the interfacial energy difference, which inevitably accompanies processing complexity. Here, a gradient random-copolymer block copolymer system, poly[(styrene-gradient-pentafluorostyrene)-b-methyl methacrylate] [P(S-g-PFS)-b-PMMA] BCP, which realizes universal vertical alignment of sub-10 nm block copolymer lamellae without any top-coat and neutral brush layers, is demonstrated. The surface energy difference between the block junction region and the tail of the gradient random-copolymer block provides a strong energetic preference for vertical lamellae on almost any type of surface, which is well supported by a thermodynamic model. Furthermore, we show that the gradient BCPs can be assembled on EUV lithography patterns to enhance their aspect ratios. This strategy of encoding surface energy balance could be potentially extended to a variety of other self-assembling systems, realizing universal orientation-controllability of nanoscale objects.

Despite the fact that research into most high-performance thermoelectric (TE) materials is focused on tellurides, compelling demand has arisen to replace tellurium (Te) with selenium (Se) due to the scarcity of Te. Silver bismuth diselenide (AgBiSe2, ABS) has been widely studied in relation to thermoelectric applications due to its intrinsically low thermal conductivity. However, its low power factor (PF) has been considered as an underlying issue preventing improvements of the TE properties of ABS. Here, it is demonstrated that a high PF can be achieved by incorporating Cu into the ABS system via the nestification of conduction bands when a disordering between Ag and Bi occurs. Degenerate electronic bands simultaneously increase the density-of-states effective mass and carrier concentration while not reducing the carrier mobility significantly. Therefore, improved TE performance with a maximum PF of 8.2 μW cm−1 K−2 and a peak zT value of 1.14 was achieved at 773 K, opening a new horizon for the development of environmentally benign TE materials with high performance capabilities.

Charge carrier transport and corresponding thermoelectric properties are often affected by several parameters, necessitating a thorough comparative study for a profound understanding of the detailed conduction mechanism. Here, as a model system, we compare the electronic transport properties of two layered semiconductors, Sb

The electrical control of antiferromagnetic moments is a key technological goal of antiferromagnet-based spintronics, which promises favourable device characteristics such as ultrafast operation and high-density integration as compared to conventional ferromagnet-based devices. To date, the manipulation of antiferromagnetic moments by electric current has been demonstrated in epitaxial antiferromagnets with broken inversion symmetry or antiferromagnets interfaced with a heavy metal, in which spin-orbit torque (SOT) drives the antiferromagnetic domain wall. Here, we report current-induced manipulation of the exchange bias in IrMn/NiFe bilayers without a heavy metal. We show that the direction of the exchange bias is gradually modulated up to ±22 degrees by an in-plane current, which is independent of the NiFe thickness. This suggests that spin currents arising in the IrMn layer exert SOTs on uncompensated antiferromagnetic moments at the interface which then rotate the antiferromagnetic moments. Furthermore, the memristive features are preserved in sub-micron devices, facilitating nanoscale multi-level antiferromagnetic spintronic devices., Antiferromagnets have great promise for spin-based information processing, offering both high operation speed, and an immunity to stray fields. Here, Kang et al demonstrate electrical manipulation of the exchange-bias, without the need for a heavy metal layer.

Description, Thermodynamically unstable nanoscale grains can be stabilized by tuning the metal-to-oxygen ratio in metal oxide nanoribbons., Nanograined metal oxides are requisite for diverse applications that use large surface area, such as gas sensors and catalysts. However, nanoscale grains are thermodynamically unstable and tend to coarsen at elevated temperatures. Here, we report effective grain growth suppression in metal oxide nanoribbons annealed at high temperature (900°C) by tuning the metal-to-oxygen ratio and confining the nanoribbons. Despite the high annealing temperatures, the average grain size was maintained at ~6 nm, which also retained their structural integrity. We observe that excess oxygen in amorphous tin oxide nanoribbons prevents merging of small grains during crystallization, leading to suppressed grain growth. As an exemplary application, we demonstrate a gas sensor using grain growth–suppressed tin oxide nanoribbons, which exhibited both high sensitivity and unusual long-term operation stability. Our findings provide a previously unknown pathway to simultaneously achieve high performance and excellent thermal stability in nanograined metal oxide nanostructures.

Surface‐Enhanced Raman Spectroscopy In article number 2100640, Yeon Sik Jung, In‐Hwan Lee, and co‐workers demonstrate detection of antibiotics present in aqueous solutions via surface‐enhanced Raman spectroscopy without using any Raman reporter molecules. Using the solvent‐assisted nanotransfer printing technique, ultrafine Ag nanowires are conformally printed on GaN nanopillars to form a metal/semiconductor hybrid structure, which achieves a significant improvement of Raman signals. [Image: see text]

Thermoelectric properties are frequently manipulated by introducing point defects into a matrix. However, these properties often change in unfavorable directions owing to the spontaneous formation of vacancies at high temperatures. Although it is crucial to maintain high thermoelectric performance over a broad temperature range, the suppression of vacancies is challenging since their formation is thermodynamically preferred. In this study, using PbTe as a model system, it is demonstrated that a high thermoelectric dimensionless figure of merit, zT ≈ 2.1 at 723 K, can be achieved by suppressing the vacancy formation via dopant balancing. Hole‐killer Te vacancies are suppressed by Ag doping because of the increased electron chemical potential. As a result, the re‐dissolution of Na2Te above 623 K can significantly increase the hole concentration and suppress the drop in the power factor. Furthermore, point defect scattering in material systems significantly reduces lattice thermal conductivity. The synergy between defect and carrier engineering offers a pathway for achieving a high thermoelectric performance by alleviating the power factor drop and can be utilized to enhance thermoelectric properties of thermoelectric materials., Charge compensation by intrinsic defects poses a big challenge for active tuning of the carrier concentration via temperature‐activated doping. By regulating Te vacancies in a p‐type PbTe via Ag doping, it is demonstrated that a synergistic interplay between a rebounding power factor and suppressed lattice thermal conductivity can improve thermoelectric performance.

Universal and fast bacterial detection technology is imperative for food safety analyses and diagnosis of infectious diseases. Although surface-enhanced Raman spectroscopy (SERS) has recently emerged as a powerful solution for detecting diverse microorganisms, its widespread application has been hampered by strong signals from surrounding media that overwhelm target signals and require time-consuming and tedious bacterial separation steps. By using SERS analysis boosted with a newly proposed deep learning model named dual-branch wide-kernel network (DualWKNet), a markedly simpler, faster, and effective route to classify signals of two common bacteria E. coli and S. epidermidis and their resident media without any separation procedures is demonstrated. With outstanding classification accuracies up to 98%, the synergistic combination of SERS and deep learning serves as an effective platform for "separation-free" detection of bacteria in arbitrary media with short data acquisition times and small amounts of training data.

Increasing renewable energy penetration rate in a power grid leads to an increase in the variability of the generated energy, which increases the system integration cost. To handle the output variations in the generation, it is necessary to secure sufficient flexible resources, such as energy storage units. Flexible resources can adjust the output quickly, which helps to increase the system flexibility. However, the electricity generation cost of the flexible resources is usually high. Because the renewable energy expansion policy is being implemented worldwide, it is necessary to evaluate the ability to manage the short-term variations of the renewable energy outputs to obtain a cost-effective long-term plan. In this study, the variability of renewable energy in Korea over the past five years was analyzed. Additionally, the backup capacity is determined to manage the variability of renewable energy output. The backup capacity is affected by system flexibility. In general, increasing system flexibility decreases the backup capacity and increases the total electricity production cost. In this study, a backup capacity planning method is proposed considering the short-term variability of renewable energy output and flexibility deficit in a power system. The numerical results illustrated the effectiveness of the proposed backup capacity planning method.

Although hexagonal boron nitride (BN) nanostructures have recently received significant attention due to their unique physical and chemical properties, their applications have been limited by a lack of processability and poor film quality. In this study, a versatile method to transfer-print high-quality BN films composed of densely stacked BN nanosheets based on a desolvation-induced adhesion switching (DIAS) mechanism is developed. It is shown that edge functionalization of BN sheets and rational selection of membrane surface energy combined with systematic control of solvation and desolvation status enable extensive tunability of interfacial interactions at BN-BN, BN-membrane, and BN-substrate boundaries. Therefore, without incorporating any additives in the BN film and applying any surface treatment on target substrates, DIAS achieves a near 100% transfer yield of pure BN films on diverse substrates, including substrates containing significant surface irregularities. The printed BNs demonstrate high optical transparency (>90%) and excellent thermal conductivity (>167 W m-1 K-1) for few-micrometer-thick films due to their dense and well-ordered microstructures. In addition to outstanding heat dissipation capability, substantial optical enhancement effects are confirmed for light-emitting, photoluminescent, and photovoltaic devices, demonstrating their remarkable promise for next-generation optoelectronic device platforms.

The conversion efficiency of the thermoelectric generator (TEG) is adversely affected by the quality of thermal contact between the module and the heat source. TEGs with the planar substrate are not suitable for the curved heat sources. Several attempts have been made to tackle this issue by fabricating complex tubular-shaped TEGs, however, all efforts have been limited to low-temperature applications. Furthermore, the electrical contact resistance of the module is critical to achieving a high-power output. In this work, we developed the tubular TEG with significantly low specific contact resistance by optimizing the joining process. We show that the modified resistance welding (MRW) performed by spark plasma sintering (SPS) is an efficient joining method for the fabrication of the TE module, with high feasibility and scalability. This research seeks to suggest important design rules to consider when fabricating TEGs.

Memory-augmented neural networks are getting more attention from many researchers as they can make an inference with the previous history stored in memory. Especially, among these memory-augmented neural networks, memory networks are known for their huge reasoning power and capability to learn from a large number of inputs rather than other networks. As the size of input datasets rapidly grows, the necessity of large-scale memory networks continuously arises. Such large-scale memory networks provide excellent reasoning power; however, the current computer infrastructure cannot achieve scalable performance due to its limited system architecture. In this paper, we propose MnnFast, a novel system architecture for large-scale memory networks to achieve fast and scalable reasoning performance. We identify the performance problems of the current architecture by conducting extensive performance bottleneck analysis. Our in-depth analysis indicates that the current architecture suffers from three major performance problems: high memory bandwidth consumption, heavy computation, and cache contention. To overcome these performance problems, we propose three novel optimizations. First, to reduce the memory bandwidth consumption, we propose a new column-based algorithm with streaming which minimizes the size of data spills and hides most of the off-chip memory accessing overhead. Second, to decrease the high computational overhead, we propose a zero-skipping optimization to bypass a large amount of output computation. Lastly, to eliminate the cache contention, we propose an embedding cache dedicated to efficiently cache the embedding matrix. Our evaluations show that MnnFast is significantly effective in various types of hardware: CPU, GPU, and FPGA. MnnFast improves the overall throughput by up to 5.38×, 4.34×, and 2.01× on CPU, GPU, and FPGA respectively. Also, compared to CPU-based MnnFast, our FPGA-based MnnFast achieves 6.54× higher energy efficiency.

Environmentally friendly ZnSe/ZnS core/shell quantum dots (QDs) as an alternative blue emission material to Cd-based QDs have shown great potential for use in next-generation displays. However, it remains still challenging to realize a high-efficiency quantum dot light-emitting diode (QLED) based on ZnSe/ZnS QDs due to their insufficient electrical characteristics, such as excessively high electron mobility (compared to the hole mobility) and the deep-lying valence band. In this work, the effects of QDs doped with hole transport materials (hybrid QDs) on the electrical characteristics of a QLED are investigated. These hybrid QDs show a p-type doping effect, which leads to a change in the density of the carriers. Specifically, the hybrid QDs can balance electrons and holes by suppressing the overflow of electrons and improving injection of holes, respectively. These electrical characteristics help to improve device performance. In detail, an external quantum efficiency (EQE) of 6.88% is achieved with the hybrid QDs. This is increased by 180% compared to a device with pure ZnSe/ZnS QDs (EQE of 2.46%). This record is the highest among deep-blue Cd-free QLED devices. These findings provide the importance of p-type doping effect in QD layers and guidance for the study of the electrical properties of QDs.

Graphics Processing Unit (GPU) vendors have been scaling singleGPU architectures to satisfy the ever-increasing user demands for faster graphics processing. However, as it gets extremely difficult to further scale single-GPU architectures, the vendors are aiming to achieve the scaled performance by simultaneously using multiple GPUs connected with newly developed, fast inter-GPU networks (e.g., NVIDIA NVLink, AMD XDMA). With fast inter-GPU networks, it is now promising to employ split frame rendering (SFR) which improves both frame rate and single-frame latency by assigning disjoint regions of a frame to different GPUs. Unfortunately, the scalability of current SFR implementations is seriously limited as they suffer from a large amount of redundant computation among GPUs. This paper proposes GPUpd, a novel multi-GPU architecture for fast and scalable SFR. With small hardware extensions, GPUpd introduces a new graphics pipeline stage called Cooperative Projection & Distribution (C-PD) where all GPUs cooperatively project 3D objects to 2D screen and effciently redistribute the objects to their corresponding GPUs. C-PD not only eliminates the redundant computation among GPUs, but also incurs minimal inter-GPU network traffic by transferring object IDs instead of mid-pipeline outcomes between GPUs. To further reduce the redistribution overheads, GPUpd minimizes inter-GPU synchronizations by implementing batching and runahead-execution of draw commands. Our detailed cycle-level simulations with 8 real-world game traces show that GPUpd achieves a geomean speedup of $4.98 \times$ in single-frame latency with 16 GPUs, whereas the current SFR implementations achieve only $3.07 \times$ geomean speedup which saturates on 4 or more GPUs. CCS CONCEPTS • Computing methodologies $\rightarrow$ Graphics processors; • Computer systems organization $\rightarrow$ Distributed architectures

Computer architects use a variety of workloads to measure system performance. For many workloads, the workload configuration determines the stress applied to the system and the corresponding performance behavior. Therefore, architects must make great efforts to explore and find the correct workload configuration before performing detailed analysis. However, such explorations become impossible for indevelopment systems which exist only as a software model. The existing system modeling platforms are either accurate but too slow, or fast but inaccurate to get workload-reported performance metrics (e.g., latency and throughput) which are necessary for configuring workloads. In this paper, we propose StressRight, a method to quickly model the first-order performance of full-system workloads and reconstruct the workload-reported performance metrics. Stress-Right allows to explore how the workload configurations affect the stress and performance. The key idea is to execute workloads on a fast but timing-agnostic platform (e.g. emulators), and efficiently reconstruct the timing/performance details by analyzing only the unique code blocks. Our evaluation using memcached and PARSEC shows that StressRight achieves 8∼45x speedup compared to a cycle-level simulator while maintaining good accuracy.

CPU architects perform a series of slow timing simulations to explore large processor design space. To minimize the exploration overhead, architects make their best efforts to accelerate each simulation step as well as reduce the number of simulations by predicting the exact performance of designs. However, the existing methods are either too slow to overcome the large number of design points, or inaccurate to safely substitute extra simulation steps with performance predictions. In this paper, we propose RpStacks, a fast and accurate processor design space exploration method to 1) identify the current design point's key performance bottlenecks and 2) estimate the exact impacts of latency adjustments without launching an extra step of simulations. The key idea is to selectively collect the information about performance-critical events from a single simulation, construct a small number of event stacks describing the latency of distinctive execution paths, and estimate the overall performance as well as stall-event composition using the stacks. Our proposed method significantly outperforms the existing design space exploration methods in terms of both the latency and the accuracy. For investigating 1,000 design points, RpStacks achieves 26 times speedup on average over a variety of applications while showing high accuracy, when compared to a popular x86 timing simulator.