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This paper investigates the impact of the thyristor commutation time on the peak currents and the active-power capability of the hybrid alternate-common-arm converter (HACC). This converter employs director thyristors for the alternate connection of a common arm in parallel to the main arms. The parallel connection enables current sharing among the arms, which allows the HACC to transfer higher output power without increasing the peak arm current. It is shown that the active-power capability of the HACC is doubled for a certain current-sharing factor, which, however, is altered by the thyristor commutation time. Therefore, the impact of the commutation time on the active-power capability of the HACC is investigated theoretically. Finally, this analysis is verified by simulation results., QC 20200217

Nowadays, some Multi-terminal DC (MTDC) systems are in operation around the world. Soon, MTDC grids will be built and overlay the present AC grids. The main driver for the construction of such a grid is to facilitate large-scale integration of remote renewable energy sources to existing AC grids and to develop the energy market. This paper presents a comprehensive analogy between the control and operation aspects of the emerging MTDC grids to those of the traditional AC power grids. Similarities and difference between the two technologies are presented and highlighted. Based on the performed detailed overview, even though a three-layered control system, i.e., primary, secondary, and tertiary control layers is state-of-the-art in large-scale AC power systems, a two-layered control system will satisfy MTDC grids control and operation requirements. This paper also addresses some control and operational issues and limitations of MTDC grids.

© 1986-2012 IEEE. The papers in this special section brings together papers focused on the recent advancements and breakthroughs in the technology of modeling and enhanced active/reactive power control of wind power conversion systems, ranging from components of wind turbines to wind farms.

Design, Control and Application of Modular Multilevel Converters for HVDC Transmission Systems is a comprehensive guide to semiconductor technologies applicable for MMC design, component sizing control, modulation, and application of the MMC technology for HVDC transmission. Separated into three distinct parts, the first offers an overview of MMC technology, including information on converter component sizing, Control and Communication, Protection and Fault Management, and Generic Modelling and Simulation. The second covers the applications of MMC in offshore WPP, including planning, technical and economic requirements and optimization options, fault management, dynamic and transient stability. Finally, the third chapter explores the applications of MMC in HVDC transmission and Multi Terminal configurations, including Supergrids. Key features: Unique coverage of the offshore application and optimization of MMC-HVDC schemes for the export of offshore wind energy to the mainland. Comprehensive explanation of MMC application in HVDC and MTDC transmission technology. Detailed description of MMC components, control and modulation, different modeling approaches, converter dynamics under steady-state and fault contingencies including application and housing of MMC in HVDC schemes for onshore and offshore. Analysis of DC fault detection and protection technologies, system studies required for the integration of HVDC terminals to offshore wind power plants, and commissioning procedures for onshore and offshore HVDC terminals. A set of self-explanatory simulation models for HVDC test cases is available to download from the companion website. This book provides essential reading for graduate students and researchers, as well as field engineers and professionals who require an in-depth understanding of MMC technology., Export Date: 22 May 2017; Book; Correspondence Address: Sharifabadi, K.; Research and Technology, Statoil ASA, Norway. QC 20170612

The energy variations in each arm of the modular multilevel converter comprises two components. The first component relates to the difference between the instantaneous input and output power of each phase-leg, and the second component relates to the energy which is moved back and forth between the two arms of the phase-leg. The latter component can be reduced or even eliminated if the peak-to-peak amplitude of the alternating voltage is greater than the pole-to-pole voltage of the dc link. This will, however, require submodules which can insert negative voltages. Therefore, a semi-full-bridge submodule which uses less semiconductors than the conventional full-bridge is proposed. Simulation results shows that by using the negative voltage-levels the capacitor voltage ripple can be reduced by up to 59%. Experimental results also shows that a 7-level voltage waveform can be generated using only one semi-full-bridge submodule with two capacitors per arm., QC 20160226

This paper deals with low-voltage ride-through (LVRT) capability of wind turbines (WTs) and in particular those driven by a doubly-fed induction generator (DFIG). This is one of the biggest challenges facing massive deployment of wind farms. With increasing penetration of WTs in the grid, grid connection codes in most countries require that WTs should remain connected to the grid to maintain the reliability during and after a short-term fault. This results in LVRT with only 15% remaining voltage at the point of common coupling (PCC), possibly even less. In addition, it is required for WTs to contribute to system stability during and after fault clearance. To fulfill the LVRT requirement for DFIG-based WTs, there are two problems to be addressed, namely, rotor inrush current that may exceed the converter limit and the dc-link overvoltage. Further, it is required to limit the DFIG transient response oscillations during the voltage sag to increase the gear lifetime and generator reliability. There is a rich literature addressing countermeasures for LVRT capability enhancement in DFIGs; this paper is therefore intended as a comprehensive state-of-the-art review of solutions to the LVRT issue. Moreover, attempts are made to highlight future issues so as to index some emerging solutions.

In this paper, a variant of the well-known voltage model is applied to rotor position estimation for sensorless control of nonsalient permanent-magnet synchronous motors (PMSMs). Particular focus is on a low-speed operation. It is shown that a guaranteed synchronization from any initial rotor position and stable reversal of rotation can be accomplished, in both cases under load. Stable rotation reversal is accomplished by making the estimator insensitive to the stator resistance. It is also shown that the closed-loop speed dynamics are similar to those of a sensored drive for speeds above approximately 0.1 per unit, provided that the model stator inductance is underestimated. Experimental results support the theory., QC 20100525, QC 20111108

In this paper, an improved phase-locked-loop-type speed and position estimator for permanent-magnet synchronous motor (PMSM) drives is considered. Particular attention is put on salient-rotor PMSMs with fast mechanical dynamics. A method is presented, whereby significantly improved tracking is achieved. While saliency makes nominal-speed stability more difficult to guarantee (an analysis of this is presented), a benefit is that signal-injection methods can be used at low speeds for accurate position estimation, which is also included in the modified estimator., QC 20100525

This paper considerspost-faultoperationof permanent-magnet synchronous motordrivesequipped with afault-tolerantinverter. Inpost-faultmode, the faulted phase is isolated and the neutral point is connected either to an additionalinverterleg or to the midpoint of the dc bus. Different methods of controlling the neutral point voltage are presented and compared. Furthermore,operationwithout a position sensor (i.e., sensorless control) is considered and a modification to an estimator previously reported in the literature is proposed in order to take into account the effect of the asymmetry introduced due to the isolation of the faulted phase inpost-faultmode. Simulations and experimental results are provided to support the theory and demonstrate the practical impact of the modifications proposed., QC 20120119

This paper proposes control algorithms for a fault-tolerant permanent-magnet synchronous motor (PMSM) drive. In order to improve the reliability of the drive, an algorithm for achieving sensorless control that operates properly also in fault mode is proposed. Furthermore, it is shown how a closed-loop field-weakening controller needs to be modified in order to operate properly in fault mode. The application in mind is electric vehicle propulsion and the algorithms presented are verified with experimental results using an in-wheel PMSM. With the proposed modifications, the reliability of the drive can be increased., QC 20120119

This paper considers the implementation of a speed and position estimator for a permanent-magnet synchronous machine in a hybrid-electric vehicle application. A modified variant of the estimator of phase-locked loop type, previously developed by Harnefors and Nee, is presented, in order to take into account effects of saliency and operation in the whole speed region. Furthermore, design rules for all parameter settings are given. Based on drive-cycle simulations, important operating points are chosen for evaluation, with good results, on an existing experimental setup., QC 20120119

QC 20120119

In this paper, the voltage sag ride-through capabilities of the line-connected electrically excited synchronous motors with damper windings (EESMs) is investigated. Two aspects are investigated, first the capability to keep the nominal speed and second the damping of speed oscillations by controlling the flux. We will design a voltage sag ride-through controller and show through simulations that the proposed controller has good speed oscillation damping capability and that the ride-through capability is improved.

In this paper it is shown that zero-input overflow limit cycles can be suppressed in a class of lossless digital integrator (LDI) all-pass filters. namely, that introduced in [1], This holds for any filter order, provided that saturation overflow characteristics are used at the input of each delay and for certain restrictions for the multiplier values. The results are shown to apply also to lossless digital differentiator (LDD) filters. The restrictions of multiplier values have the effect of excluding certain combinations of poles within the unit circle, most of which are in the left half circle where corresponding LDD filters can be used. Asymptotic stability can be guaranteed for all second-order LDI and LDD filters., QC 20100525