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This work presents a power-efficient level crossing (LC) ADC designed to digitize sparse signals. It uses dynamically self-biased comparators, which require minimal current when the input voltage is far from a decision threshold. It also uses a DAC architecture which avoids the signal attenuation commonly present in prior LC ADC works, improving the achievable SNDR. The prototype is designed and implemented in a 65-nm CMOS technology, and occupies an area of 0.0045 mm2. In a 20 kHz bandwidth, the LC-ADC achieves a 64 dB SNDR. Thanks to the proposed techniques a power efficiency of up to 1.8 fJ/conv.-step is achieved for sinusoidal inputs. For sparse biopotential signals, a FoMW as low as 0.9 fJ/conv.-step was measured. This makes the prototype interesting for e.g., biomedical applications that make use of spike-based processing.

This paper presents a co-design of a 10-bit SAR ADC and its front-end filter. Because the SAR ADC works as a discrete-time data converter, its input signal only needs to be accurate at its sampling moment. Therefore, the filter can be switched off in the ADC conversion phase to save power. To reduce the start-up time when the filter is activated again, a low-power auxiliary amplifier is used in the ADC conversion phase to maintain the filter output roughly. A 10-bit 10 MS/s SAR ADC with such a duty-cycled multiple feedback filter is fabricated in a 65 nm CMOS technology. The filter power has been reduced by 36% thanks to the proposed duty-cycled operation. The prototype achieves 8.3 ENOB and 59.3 dB SFDR at low input frequencies, and it has 40 dB suppression at the Nyquist input frequency, while consuming 91.1 µ W.

Data-retention flip-flops (DR-FF) provide an efficient state retention capability for any processor with frequent active-to-sleep mode transitions. This brief proposes new ultra-low-power balloon-based DR-FFs operating over a wide supply voltage range achieving a sleep mode power consumption as low as 380fW, an improvement of 185× over the previously reported CMOS DR-FFs. The proposed DR-FFs have significantly lower transition mode energy consumption compared to prior-art non-volatile DR-FFs (> 18×). The proposed DR-FFs consume the lowest total energy (sleep, store and restore modes) for sleep mode times less than 520 ms. Additionally, the designed DR-FFs are comparable with most of the NV-FFs in literature for sleep times of up to 100 s, while eliminating the drawbacks of Non-volatile data retention FFs (higher/multiple supplies, integration/endurance issues).

This letter presents a dynamic resistive temperature sensor for IoT ambient temperature monitoring applications. The sensor integrates on-chip analog offset, gain, and nonlinearity correction techniques with state-of-the-art power and size performance. By shifting the reset phase of the ADC, analog offset correction is realized. By adding programmable capacitors, gain errors are corrected. By presetting and resetting a small capacitor array, the systematic nonlinearity error is mitigated. A piecewise linear approximation is adopted to reduce overhead. The temperature sensor achieves +0.7°C/-0.6°C accuracy with 2.98 pJ/conversion and 0.0023 mm2, including all corrections, resulting in a resolution FoM of 0.66 pJ K2.

This paper reviews several examples of ultra low power sensor interfaces for IoT applications. In such applications, the sensing operation is often performed at a relatively low frequency, and sometimes it is heavily duty-cycled, or it should be triggered by particular events or thresholds. The paper reviews why dynamic sensor interface architectures are a good choice in this context, and gives several design examples that can operate dynamically and that can be triggered by a single clock pulse. Suitable ADC design strategies are explained, and two exemplary sensor interfaces are described: a capacitive sensor interface, and a resistor-based temperature sensor interface including analog correction techniques. Both designs are reviewed and the main features in terms of efficiency and performance are discussed.

Objective: Sensing with capacitive electrodes is of interest for long-term, comfortable bio-potential measurements (e.g., ECG). However, due to the small body-to-electrode capacitance (C e ), the design of the associated front-end amplifier remains a challenge. Both voltage amplifiers (VA) and charge amplifiers (CA) can be employed. While basic comparisons of both typologies were done before, this paper extends the comparison to their responses to artifacts (caused by motion or interference). Further, a VA-CA-switchable amplifier is proposed, allowing to adapt the amplifier type to different situations, and enabling to estimate the body-to-electrode capacitance C e in a passive way. Methods: A VA-CA switchable amplifier was implemented in a 180 nm CMOS process. The responses to artifacts for VA and CA were studied by modelling, simulations and experiments using the custom IC. The proposed C e estimation method was validated by electrical tests and in-vivo tests. Results: VAs are less affected by C e variation artifacts, while CAs recover faster from triboelectricity artifacts. In a VA, these two artifacts are multiplicative and get modulated if they occur simultaneously, but in a CA they remain independent. Conclusion: The combined VA-CA amplifier has the potential for optimal amplifier selection according to the properties of the recorded signal, the value of C e and the actual presence of artifacts. Moreover, it can estimate C e without extra hardware. Significance: The proposed VA-CA switchable structure is superior to an individual VA or CA, thanks its adaptability to signal quality and artifacts, and it provides extra information on the body-to-electrode interface quality (C e ).

Nowadays, many battery-operated SoCs for loT and environmental monitoring applications are equipped with temperature sensors. In these miniaturized systems, power and area are two critical concerns. One challenge for temperature sensors is that they are sensitive to process corners and random mismatch. Generally, a 2-point trim and systematic non-linear error removal are required, especially for resistor-based sensing front-ends with two types of resistors, whose spread is partially uncorrelated [1], [2]. These corrections are done off-chip and digitally in most publications. In particular for low power sensors, they may consume more power and area than the sensor itself when integrated on-chip [3]. This work presents a resistive temperature sensor that integrates on-chip analog offset, gain and non-linearity correction techniques, while keeping state-of-the-art power and size performance. The prototype consumes 2.98pJ/conversion with an area of 0. 0023textmm 2 including all the correction techniques and achieves +0.7/-0.6 circC inaccuracy.