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Electrical properties of two-dimensional and three-dimensional SrBi2Ta2O9 (SBT)-based ferroelectric capacitors are compared after integration. Ferroelectric contribution of the sidewall SBT in three-dimensional configuration is revealed to be strongly dependent on the Bi segregation occurring in the sidewall region during metal-organic chemical-vapor deposition (MOCVD) of the SBT layer.

The report stated that the key assumption in this model is that the trap-trap distance or trap-interface distance is the dominant parameter in the conduction mechanism causing anomalous charge loss. The oxide is characterized by a single parameter, the trap density. The studies stated that failure rate calculations are possible for different oxide qualities, thicknesses and voltage. Two-trap and three-trap percolation paths can limit the failure rate.

Examination of the influence of device geometry and applied programming voltages on the performance of a split-gate flash EEPROM cell referred as high injection MOS (HIMOS) indicates that a cell area of 16.5 micro square meter exhibits ability to achieve microsecond programming with a program-gate voltage of 12 V and 5 V-only operation. The HIMOS cell exhibits a very low drain current and uses a lower power consumption during programming. Experimental studies reveal the viability of 3.3 V-only operation in 0.7-micrometer technology. The HIMOS cell can be used for embedded memory applications.

The oxidation characteristics of TiAlN films integrated in the bottom electrode (BE) stack of three-dimensional SrBi2Ta2O9-based (SBT) ferroelectric capacitors are investigated in the range of 650–800 °C. The patterned TiAlN\Ir\IrO2\Pt BE is encapsulated by a thin ferroelectric SBT film deposited by metal organic chemical vapor deposition and then crystallized ex situ at temperatures higher than 650 °C in oxygen. During this annealing step the TiAlN film oxidizes from the lateral side of the patterned BE mesas. Compared to the vertical oxidation in blanket TiAlN layers, the lateral oxidation rate in our capped patterned films is much larger for similar oxidation conditions. This lateral oxidation of the TiAlN is strongly correlated with the in-film SBT stress that depends upon the deposition temperature and the thickness of the SBT film: the higher the tensile stress in the SBT, the larger the TiAlN oxidation length induced. From a kinetic study, the lateral oxygen diffusion was found to be a self-limited process with activation energy of about 2.2 eV and a preexponential factor D0 of 7×10-3 cm2/s. This factor, one to two orders of magnitude higher than the one obtained in blanket TiAlN layers, is indicative of interfacial diffusion. The mechanism of the increased lateral oxidation can be understood by the high tensile stress of the SBT film at the sidewall of the ferroelectric capacitors that tends to tear apart the Ir/TiAlN interface and causes enlarged interfacial oxygen diffusion. The limiting step of the oxidation mechanism is identified as oxygen diffusion in the Al-depleted/Ti-rich TiAlN layer that lies beyond the Al-rich film found at the very edge of the capacitors, whereas on blanket films the oxygen diffusion is limited in the Al-rich surface layer region. [ABSTRACT FROM AUTHOR]

Ferroelectric random access memory (FeRAM) is an attractive candidate technology for embedded nonvolatile memory, especially in applications where low power and high program speed are important. Market introduction of high-density FeRAM is, however, lagging behind standard complementary metal-oxide semiconductor (CMOS) because of the difficult integration technology. This paper discusses the major integration issues for high-density FeRAM, based on SrBi2Ta2O9 (strontium bismuth tantalate or SBT), in relation to the fabrication of our stacked cell structure. We have worked in the previous years on the development of SBT-FeRAM integration technology, based on a so-called pseudo-three-dimensional (3D) cell, with a capacitor that can be scaled from quasi two-dimensional towards a true three-dimensional capacitor where the sidewalls will importantly contribute to the signal. In the first phase of our integration development, we integrated our FeRAM cell in a 0.35 μm CMOS technology. In a second phase, then, possibility of scaling of our cell is demonstrated in 0.18 μm technology. The excellent electrical and reliability properties of the small integrated ferroelectric capacitors prove the feasibility of the technology, while the verification of the potential 3D effect confirms the basic scaling potential of our concept beyond that of the single-mask capacitor. The paper outlines the different material and technological challenges, and working solutions are demonstrated. While some issues are specific to our own cell, many are applicable to different stacked FeRAM cell concepts, or will become more general concerns when more developments are moving into 3D structures. [ABSTRACT FROM AUTHOR]

The difficult scaling of ferroelectric random access memories with the complementary metal-oxide semiconductor technology roadmap requires integration of three-dimensional (3D) ferroelectric capacitors (FeCAP’s). In this work the unusual electrical behavior of 3D FeCAP sidewalls was studied by comparing the electrical properties of two-dimensional and 3D integrated FeCAP structures. We evidenced composition variations of the SrBi2Ta2O9 (SBT) film in the sidewalls with marked bismuth segregation during metal-organic chemical-vapor deposition (MOCVD) of the SBT film. The segregation was reduced after decreasing the deposition temperature from 440 °C, whereby the Bi-rich phase in the sidewalls does not contribute to polarization, down to 405 °C, whereby sidewall SBT contributes to polarization. After further optimization of the MOCVD conditions at 405 °C, the segregation is minimized and the ferroelectric contribution of the sidewall SBT is almost the same as the contribution of the planar SBT. As a result, 3D FeCAP’s integrated up to metal interconnection exhibit a remnant polarization Pr∼7.5 μC/cm2. [ABSTRACT FROM AUTHOR]